Data storage devices having scale-out devices to map and control groups of non-volatile memory devices

1. A scale-out device for controlling a first group of non-volatile memory devices from among a plurality of groups of non-volatile memory devices at a data storage device, the scale-out device comprising:

a buffer configured to store address mapping information mapping logical block addresses to physical page numbers for the first group of non-volatile memory devices, wherein the buffer does not store address mapping information for other groups of non-volatile memory devices among the plurality of groups of non-volatile memory devices at the data storage device; and

a scale-out controller configured to control operation of only the first group of non-volatile memory devices, independently of the other groups of non-volatile memory devices, according to the address mapping information stored at the buffer, wherein

the scale-out controller is connected to a first set of two or more non-volatile memory devices, from among the first group of non-volatile memory devices, via a first channel, and

the scale-out controller is connected to a second set of two or more non-volatile memory devices, from among the first group of non-volatile memory devices, via a second channel.

2. The scale-out device of claim 1 , wherein the buffer is configured to store address mapping information for only the first group of non-volatile memory devices from among the plurality of groups of non-volatile memory devices.

3. The scale-out device of claim 1 , wherein the buffer and the scale-out controller are included in a multi-chip package (MCP).

4. A memory module comprising:

a first scale-out device coupled to a first group of non-volatile memory devices from among a plurality of groups of non-volatile memory devices, the first scale-out device being configured to

store a first set of address mapping information mapping a first set of logical block addresses to a first set of physical page numbers for the first group of non-volatile memory devices, and

control operation of only the first group of non-volatile memory devices according to the first set of address mapping information, wherein

the first scale-out device is connected to a first set of two or more non-volatile memory devices, from among the first group of non-volatile memory devices, via a first channel, and

the first scale-out device is connected to a second set of two or more non-volatile memory devices, from among the first group of non-volatile memory devices, via a second channel; and

a second scale-out device coupled to a second group of non-volatile memory devices from among the plurality of groups of non-volatile memory devices, the second scale-out device being configured to

store a second set of address mapping information mapping a second set of logical block addresses to a second set of physical page numbers for the second group of non-volatile memory devices, and

control operation of only the second group of non-volatile memory devices according to the second set of address mapping information, wherein

the second scale-out device is connected to a third set of two or more non-volatile memory devices, from among the second group of non-volatile memory devices, via a third channel, and

the second scale-out device is connected to a fourth set of two or more non-volatile memory devices, from among the second group of non-volatile memory devices, via a fourth channel.

5. The memory module of claim 4 , further comprising:

the first group of non-volatile memory devices.

6. The memory module of claim 5 , wherein the first scale-out device is configured to store address mapping information for only the first group of non-volatile memory devices.

7. The memory module of claim 5 , wherein the first scale-out device is included in a multi-chip package (MCP).

8. The memory module of claim 5 , further comprising:

the second group of non-volatile memory devices.

9. The memory module of claim 8 , wherein the second scale-out device is configured to store address mapping information for only the second group of non-volatile memory devices.

10. A data storage device comprising:

a memory cluster including at least a first memory group and a first scale-out device, the first memory group including at least a first plurality of non-volatile memories, and the first scale-out device including a first local flash translation layer configured to associate a first set of logical block addresses for the data storage device with a first set of physical page numbers for the first plurality of non-volatile memories; and

a memory controller including a global flash translation layer configured to allocate the first set of logical block addresses to the first scale-out device using a table stored in an external buffer coupled to the memory controller, wherein the table associates the first set of logical block addresses with an identifier of a first scale-out controller of the first scale-out device and the table does not store the first set of physical page numbers for the first plurality of non-volatile memories.

11. The data storage device of claim 10 , wherein the data storage device is a Universal Flash Storage (UFS) device.

12. The data storage device of claim 10 , wherein

the first scale-out device comprises a first buffer configured to store first address mapping information for the first set of logical block addresses and the first set of physical page numbers; and

the first scale-out controller is configured to control operation of only the first plurality of non-volatile memories according to the first address mapping information stored at the first buffer.

13. The data storage device of claim 10 , wherein the first plurality of non-volatile memories includes a first plurality of groups of non-volatile memory devices, each group of non-volatile memory devices in the first plurality of groups of non-volatile memory devices being coupled to the first scale-out device via a corresponding one of a plurality of first channels.

14. The data storage device of claim 10 , wherein

the memory cluster further includes a second memory group and a second scale-out device, the second memory group including at least a second plurality of non-volatile memories, and the second scale-out device including a second local flash translation layer configured to associate a second set of logical block addresses for the data storage device with a second set of physical page numbers for the second plurality of non-volatile memories; and

the global flash translation layer of the memory controller is further configured to allocate the second set of logical block addresses to the second scale-out device using the table stored in the external buffer coupled to the memory controller, wherein the table associates the second set of logical block addresses with an identifier of a second scale-out controller of the second scale-out device and the table does not store the second set of physical page numbers for the second plurality of non-volatile memories.

15. The data storage device of claim 14 , wherein

the second scale-out device comprises a second buffer configured to store second address mapping information for the second set of logical block addresses and the second set of physical page numbers; and

the second scale-out controller is configured to control operation of only the second plurality of non-volatile memories according to the second address mapping information stored at the second buffer.

16. The data storage device of claim 14 , wherein the second plurality of non-volatile memories includes a second plurality of groups of non-volatile memory devices, each group of non-volatile memory devices in the second plurality of groups of non-volatile memory devices being coupled to the second scale-out device via a corresponding one of a plurality of second channels.