Method, apparatus and computer program for management of flash memory

1. A system on chip for managing memory, the system on chip comprising:

a memory information read unit configured to read standard integrated information using a first instruction or read standard information using a second instruction from at least one of the memory and an application image; and

a memory feature setting unit configured to set a feature of the memory using the standard integrated information or the standard information, wherein the memory feature setting unit selects all or some of a plurality of bus access modes defined in the standard integrated information or in the standard information and sets a bus access mode of the memory as one of all or some of the bus access modes, wherein the plurality of defined bus access modes are formed by combining one or more pins associated with a command, one or more pins associated with an address, and one or more pins associated with data.

2. The system on chip of claim 1 , wherein the first instruction and the second instruction are different from each other.

3. The system on chip of claim 1 , wherein the standard integrated information comprises a pseudo basic parameter table, an additional parameter table, and a comprehensive command table.

4. The system on chip of claim 1 , wherein the memory feature setting unit sets a protection function of the memory as at least one of a plurality of protection types defined in the standard integrated information or the standard information.

5. The system on chip of claim 1 , wherein the memory feature setting unit sets a sector map of the memory as at least one of a plurality of sector units defined in the standard integrated information or the standard information.

6. The system on chip of claim 1 , further comprising a memory information determination unit configured to determine whether the standard integrated information is present or configured to determine whether the standard information corresponds to a designated model or undesignated model.

7. The system on chip of claim 1 , further comprising a memory information write unit configured to write or change all or some of the standard integrated information in at least one of the memory and the application image.

8. The system on chip of claim 1 , further comprising a command execution unit configured to execute a command defined in the standard integrated information.

9. The system on chip of claim 1 , wherein the standard integrated information comprises a pseudo basic parameter table, an additional parameter table, and a comprehensive command table.

10. A method of managing memory using a memory management apparatus, the method comprising:

determining whether standard integrated information is present by a memory information determination unit;

reading the standard integrated information from at least one of the memory and an application image using a first instruction by a memory information read unit if the standard integrated information is present;

setting a feature of the memory using the standard integrated information by a memory feature setting unit;

selecting all or some of a plurality of bus access modes defined in the standard integrated information by the memory feature setting unit;

setting a bus access mode of the memory as one of all or some of the bus access modes by the memory feature setting unit; and

forming the plurality of defined bus access modes by combining one or more pins associated with a command, one or more pins associated with an address, and one or more pins associated with data.

11. The method of claim 10 , further comprising reading standard information from at least one of the memory and the application image using a second instruction when the standard integrated information is not present.

12. The method of claim 11 , further comprising:

determining whether the standard information corresponds to a designated model; and

setting the feature of the memory using the standard information when the standard information corresponds to the designated model.

13. The method of claim 10 , further comprising writing or changing all or some of the standard integrated information in at least one of the memory and the application image.

14. The method of claim 10 ,

wherein the standard integrated information comprises a pseudo basic parameter table, an additional parameter table, and a comprehensive command table.

15. A non-transitory computer-readable medium managing memory, the non-transitory computer-readable medium comprising computer program instructions, the computer program instructions performing a process when executed by a processor, the process comprising:

determining whether standard integrated information is present by a memory information determination unit

reading the standard integrated information from at least one of the memory and an application image using a first instruction by the memory information read unit if the standard integrated information is present;

setting a feature of the memory using the standard integrated information by a memory feature setting unit;

selecting all or some of a plurality of bus access modes defined in the standard integrated information by the memory feature setting unit;

setting a bus access mode of the memory as one of all or some of the bus access modes by the memory feature setting unit; and

forming the plurality of defined bus access modes by combining one or more pins associated with a command, one or more pins associated with an address, and one or more pins associated with data.

16. The non-transitory computer-readable medium of claim 15 , wherein the process further comprises

reading standard information from at least one of the memory and the application image using a second instruction when the standard integrated information is not present.