IP Library Granted Patent US 9,641,774
Granted Patent B2
US 9,641,774 · App. 15/073,600 · Granted May 2, 2017

Solid-state imaging device and imaging device

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Quick Facts
Patent No.
US 9,641,774
App. No.
15/073,600
Granted
May 2, 2017
Kind
B2
Abstract

A solid-state imaging device that suppresses streaking includes an imaging region in which unit cells are aligned in matrix, an A/D converter for converting an analog signal generated in the imaging region to a digital signal, and a ramp buffer having an input terminal and an output terminal. Ramp voltage is input to the input terminal, and a reference signal having the ramp voltage is output from the output terminal toward the A/D converter. The A/D converter includes a comparator disposed in each column for comparing an analog signal with a reference signal, and a counter disposed corresponding to the comparator for counting a comparison period of the comparator. The ramp buffer includes a feedback circuit for simultaneously outputting the reference signal to the multiple comparators and controlling the amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the terminal.

Claims (53)

1. A solid-state imaging device comprising:

a pixel section in which a plurality of pixels for conducting photoelectric conversion are arranged in matrix;

an A/D converter for converting a pixel signal generated in the pixel section from an analog signal to a digital signal in a plurality of pixel units;

a ramp generation circuit for generating ramp voltage; and

a buffer circuit having an input terminal and an output terminal, the ramp voltage generated in the ramp generation circuit being input to the input terminal and a reference signal having the ramp voltage being output from the output terminal toward the A/D converter,

wherein

the A/D converter includes:

a comparator disposed in each pixel column for comparing the analog signal of each pixel in the plurality of pixels with the reference signal, the comparator having a first input terminal to which the reference signal is input and a second input terminal to which the analog signal is input; and

a counter latch disposed corresponding to the comparator, the counter latch counting a period of comparison of the analog signal and the reference signal by the comparator, and retaining the digital signal corresponding to the period,

at least the buffer circuit or the ramp generation circuit is provided in plural number,

the first input terminal is coupled to a plurality of ramp signal lines, and

the reference signal generated from the buffer circuit and the ramp generation circuit is input to the first input terminal from the plurality of ramp signal lines.

2. The solid-state imaging device of claim 1 ,

wherein

the plurality of ramp signal lines include a first ramp signal line coupling an output terminal of a first buffer circuit and the first input terminal and a second ramp signal line coupling an output terminal of a second buffer circuit and the first input terminal, and

the A/D converter further includes:

a first capacitive element inserted in series between the first ramp signal line and the first input terminal; and

a second capacitive element inserted in series between the second ramp signal line and the first input terminal.

3. An imaging device comprising:

the solid-state imaging device of claim 1 ; and

an optical system for forming an image of a subject on the pixel section.

4. The solid-state imaging device of claim 1 ,

wherein

the buffer circuit includes a feedback circuit for simultaneously outputting the reference signal to a plurality of the comparator, and controlling an amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the output terminal.

5. The solid-state imaging device of claim 4 ,

wherein

the buffer circuit includes:

an n-type input transistor having a gate coupled to the input terminal of the buffer circuit and a source coupled to the output terminal of the buffer circuit,

an n-type current source load transistor having a drain coupled to the source of the input transistor and a source that is grounded,

a p-type current source transistor having a source coupled to a power source and a drain coupled to the drain of the input transistor, and

a p-type feedback transistor having a gate coupled to the drain of the input transistor, a source coupled to the power source, and a drain coupled to the output terminal of the buffer circuit,

a source follower circuit is configured with the input transistor and the current source load transistor, and

the feedback circuit is configured with the current source transistor and the feedback transistor.

6. The solid-state imaging device of claim 4 ,

wherein

the buffer circuit is disposed adjacent to the comparator.

7. The solid-state imaging device of claim 1 ,

wherein

the first input terminal and the output terminal of the buffer circuit are coupled by the ramp signal lines in common.

8. The solid-state imaging device of claim 7 ,

wherein

the buffer circuit includes a feedback circuit for controlling an amount of current flowing to the output terminal according to the ramp voltage of the reference signal output from the output terminal.

9. The solid-state imaging device of claim 7 ,

wherein

the comparator has a first input terminal to which the reference signal is input and a second input terminal to which the analog signal is input, and

the solid-state imaging device further includes:

a first ramp signal line coupling an output terminal of a first buffer circuit and the first input terminal of the comparator,

a second ramp signal line for coupling an output terminal of a second buffer circuit and the first input terminal of the comparator,

a first capacitive element inserted in series between the first ramp signal line and the first input terminal of the comparator, and

a second capacitive element inserted in series between the second ramp signal line and the first input terminal of the comparator.

10. The solid-state imaging device of claim 7 ,

wherein

the ramp generation circuit and the buffer circuit are coupled via a capacitive element.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 14, 2016
From: SHISHIDO, SANSHIRO; HIGUCHI, MASAHIRO; ICHIRYU, DAI; NISHIMURA, KAZUKO; ABE, YUTAKA
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 038288/0432 →