Area-efficient and robust electrostatic discharge circuit
View Patent ↗Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.
1. An apparatus comprising:
a pad;
a first transistor coupled in series with a second transistor and coupled to the pad; and
a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event, wherein the self-biasing circuit comprises a diode-connected transistor coupled to the first transistor, wherein the diode-connected transistor has a drain terminal and a gate terminal, and wherein the drain terminal is coupled to the gate terminal.
2. The apparatus of claim 1 , wherein the first and second transistors are n-type FinFETs.
3. The apparatus of claim 2 , wherein the diode-connected transistor comprises:
a source terminal coupled to the first transistor; and
a drain terminal coupled to a first power supply node.
4. The apparatus of claim 1 comprises a first diode coupled to the pad and the second transistor via a ground node.
5. The apparatus of claim 4 comprises a third transistor coupled in series with a fourth transistor and coupled to the pad.
6. The apparatus of claim 5 , wherein the third and fourth transistors are p-type FinFETs.
7. The apparatus of claim 6 , wherein the self-biasing circuit is to bias the third transistor such that the third transistor is to be weakly biased during the ESD event.
8. The apparatus of claim 7 , wherein the self-biasing circuit comprises a second diode-connected transistor with a source terminal coupled to third transistor and a drain terminal coupled to the first power supply node.
9. The apparatus of claim 8 comprises a second diode coupled to the pad and the fourth transistor via a second power supply node.
10. The apparatus of claim 9 , wherein the second power supply node is to supply a power higher than a power supplied by the first power supply node.
11. The apparatus of claim 5 comprises a first pre-driver coupled to a gate terminal of the fourth transistor.
12. The apparatus of claim 11 comprises a fifth transistor coupled in series with a sixth transistor and coupled to the pad, wherein the fifth and sixth transistors are n-type FinFETs.
13. The apparatus of claim 12 , wherein the self-biasing circuit is to bias the fifth transistor such that the fifth transistor is to be weakly biased during the ESD event.
14. The apparatus of claim 13 comprises a second pre-driver coupled to a gate terminal of the sixth transistor, wherein the first and second pre-drivers are controlled by a logic circuitry.
15. The apparatus of claim 1 , wherein the third and fourth transistors are p-type FinFETs.
16. An apparatus comprising:
a transistor; and
a local ballast resistor formed of a trench contact (TCN) layer, the local ballast resistor having a terminal coupled to either the drain or source terminal of the transistor,
wherein the local ballast resistor is coupled to a dummy via contact node (VCN) for cooling, wherein the dummy via contact node is coupled to a metal stub.
17. The apparatus of claim 16 , wherein the transistor is an n-type FinFET, and wherein a source terminal of the transistor is coupled directly or indirectly to a ground node.
18. The apparatus of claim 17 , wherein the local ballast resistor has a second terminal coupled to a pad.
19. The apparatus of claim 16 , wherein the transistor is a first transistor, wherein the local ballast resistor is a first local ballast resistor, and wherein the apparatus comprises:
a second transistor, and
a second local ballast resistor formed of a TCN layer, the second local ballast resistor having a first terminal coupled to either drain or source terminals of the second transistor.
20. The apparatus of claim 19 , wherein the second transistor has a source terminal which is directly or indirectly coupled to a power supply node, and wherein the second local ballast resistor has a second terminal coupled to the pad, wherein the second local ballast resistor is coupled to a dummy via contact node (VCN) for cooling, and wherein the dummy via is coupled to a metal stub.
21. The apparatus of claim 16 , wherein resistance of the local ballast resistor increases when the TCN is extended over one or more diffusion regions.
22. A system comprising:
an integrated circuit including:
an input-output (I/O) pad; and
an electrostatic discharge (ESD) circuit coupled to the I/O pad, wherein the ESD circuit comprises:
a first transistor coupled in series with a second transistor and coupled to the I/O pad; and
a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an ESD event, wherein the self-biasing circuit comprises a diode-connected transistor coupled to the first transistor, wherein the diode-connected transistor has a drain terminal and a gate terminal, wherein the drain terminal is coupled to the gate terminal; and
an interface to allow the integrated circuit to communicate with another device.
23. The system of claim 22 , wherein the diode-connected transistor comprises a source terminal coupled to the first transistor and a drain terminal coupled to a first power supply node.