Method and system for serialization and deserialization (SERDES) for inter-system communications
View Patent ↗An integrated circuit may comprise a tuner operable to digitize a band of frequencies comprising a plurality of television channels, a crossbar operable to select one or more of the plurality of television channels output by the tuner, a plurality of demodulators operable to receive the selected one or more television channels from the crossbar and demodulate the selected one or more television channels to recover a plurality of transport streams, a transport module operable to multiplex the plurality of transport streams into a single packet stream, and a framer operable to: encapsulate packets of the plurality of transport streams into transport stream frames of a serial datastream, and insert filler frames into the serial datastream after every Nth transport stream frame of the serial datastream, where N is an integer.
1. A system comprising:
a wideband tuner, a narrowband tuner, a crossbar, a plurality of demodulators, and a serializer, wherein:
the crossbar is operable to:
select a plurality of channels of one or more signals output by the wideband tuner and/or the narrowband tuner;
output the selected plurality of channels to the plurality of demodulators;
the plurality of demodulators are operable to demodulate the selected plurality of channels to generate a plurality of demodulated signals;
the serializer is operable to:
generate, from the plurality of demodulated signals, a serial stream of frames for transmission onto a communication medium, wherein one or more of the frames are filler frames; and
determine when to insert the filler frames in the serial stream of frames based on a parameter value stored in memory.
2. The system of claim 1 , wherein the serializer is operable to set the parameter value based on a timing mismatch between a first oscillator residing in the serializer and a second oscillator residing in a deserializer that receives the serial stream of frames via the communication medium.
3. The system of claim 1 , wherein the serializer is operable to set the parameter value during run time of the serializer.
4. The system of claim 1 , wherein the serializer is operable to set the parameter value based on a size of a buffer in a deserializer that receives the serial stream of frames via the communication medium.
5. The system of claim 1 , wherein the serializer is operable to set the parameter value based on a maximum bitrate that can be received by a deserializer that receives the serial stream of frames via the communication medium.
6. The system of claim 1 , wherein the serializer comprises a framing circuit that in turn comprises header insertion circuitry, filler bits insertion circuitry, a buffer, and control circuitry.
7. The system of claim 6 , wherein:
the header insertion circuitry is operable to generate frame headers;
the filler bits insertion circuitry is operable to generate filler bits;
the buffer is operable to buffer bits of the plurality of demodulated signals;
the control circuitry is operable to select, at any given time, whether bits from the header insertion circuitry, bits from the filler bits insertion circuitry, or bits from the buffer are placed into the serial stream of frames.
8. The system of claim 7 , wherein the control circuitry is operable to periodically select bits from the filter bits insertion circuitry.
9. The system of claim 7 , wherein a header output by the header insertion circuitry comprises one or more bits indicating whether a corresponding payload comprises filler bits, data bits, or both.
10. A method comprising:
selecting, by a crossbar circuit of an electronic device, a plurality of channels of one or more signals output by a wideband tuner of the electronic system and/or a narrowband tuner of the electronic device;
outputting, by the crossbar circuit, the selected plurality of channels to the plurality of demodulators;
demodulating, by a plurality of demodulators of the electronic device, the selected plurality of channels to generate a plurality of demodulated signals;
multiplexing, by a serializer of the electronic device, the plurality of demodulated signals into a serial stream of frames;
generating, by the serializer from the plurality of demodulated signals, a serial stream of frames for transmission onto a communication medium, wherein one or more of the frames are filler frames; and
determining, by the serializer, when to insert the filler frames in the serial stream of frames based on a parameter value stored in memory.
11. The method of claim 10 , comprising setting, by the serializer, the parameter value based on a timing mismatch between a first oscillator residing in the serializer and a second oscillator residing in a deserializer that receives the serial stream of frames via the communication medium.
12. The method of claim 11 , comprising setting, by the serializer, the parameter value during run time of the serializer.
13. The method of claim 11 , comprising setting, by the serializer, the parameter value based on a size of a buffer in a deserializer that receives the serial stream of frames via the communication medium.
14. The method of claim 11 , comprising setting, by the serializer, the parameter value based on a maximum bitrate that can be received by a deserializer that receives the serial stream of frames via the communication medium.
15. The method of claim 11 , wherein the serializer comprises a framing circuit that in turn comprises header insertion circuitry, filler bits insertion circuitry, a buffer, and control circuitry.
16. The method of claim 15 , comprising:
generating, by the header insertion circuitry, headers of the one or more frames;
generating, by the filler bits insertion circuitry, filler bits of the one or more frames;
buffering, by the buffer, bits of plurality of demodulated signals;
selecting, by the control circuitry at any given time, whether bits from the header insertion circuitry, bits from the filler bits insertion circuitry, or bits from the buffer are placed into the serial stream of frames.
17. The method of claim 16 , comprising periodically selecting, by the control circuitry, bits from the filter bits insertion circuitry.
18. The method of claim 16 , wherein a header output by the header insertion circuitry comprises one or more bits indicating whether a corresponding payload comprises filler bits, data bits, or both.