Structure of signal lines in the fan-out region of an array substrate

1. An array substrate comprising:

a surface;

a plurality of signal lines disposed on the surface in a display area;

a plurality of signal pads disposed on the surface in a non-display area; and

a fan-out portion disposed on the surface in the non-display area, the fan-out portion comprising a plurality of fan-out lines connecting the plurality of signal lines to the plurality of signal pads,

wherein each of the plurality of fan-out lines comprises:

a pattern electrically connected to a corresponding signal pad of the plurality of signal pads; and

a straight portion electrically connected to a corresponding signal line of the plurality of signal lines,

wherein the pattern comprises a first conductive layer and a third conductive layer disposed on the first conductive layer, the third conductive layer comprising a dummy electrode,

wherein the straight portion comprises the first conductive layer and a second conductive layer disposed on the first conductive layer, the third conductive layer being, in a lateral direction, spaced apart from the straight portion at a transition between the pattern and the straight portion, and

wherein a thickness of the pattern between the first conductive layer and the third conductive layer is equivalent to a thickness of the straight portion between the first conductive layer and the second conductive layer.

2. The array substrate of claim 1 , wherein:

an insulating layer is disposed between the first conductive layer and the second conductive layer; and

the second conductive layer is electrically connected to the first conductive layer via a contact.

3. The array substrate of claim 2 , wherein:

the contact comprises:

a first contact connecting a first end of the second conductive layer to the first conductive layer; and

a second contact connecting a second end of the second conductive layer to the first conductive layer; and

in the straight portion, the first conductive layer and the second conductive layer are connected in parallel.

4. The array substrate of claim 3 , wherein:

the first contact is disposed at a boundary between the pattern and the straight portion; and

a location of the first contact becomes closer to a corresponding signal pad of the plurality of signal pads from a center portion of the fan-out portion toward edges of the fan-out portion.

5. The array substrate of claim 1 , wherein resistances of the patterns reduce from a center portion of the fan-out portion toward edges of the fan-out portion.

6. The array substrate of claim 1 , wherein lengths of the straight portions increase from a center portion of the fan-out portion toward edges of the fan-out portion.

7. The array substrate of claim 1 , wherein:

the fan-out portion comprises:

a first region in which the plurality of fan-out lines are spaced from one another at a constant interval; and

a second region in which the plurality of fan-out lines are spaced from one another at gradually reducing intervals;

the pattern is disposed in the first region; and

the straight portion is disposed in the second region.

8. The array substrate of claim 1 , wherein:

the plurality of signal lines comprise:

a plurality of gate lines extending in a first direction; and

a plurality of data lines extending in a second direction crossing the first direction;

the first conductive layer is disposed at a same layer as the plurality of gate lines; and

the second conductive layer is disposed at a same layer as the plurality of data lines.

9. The array substrate of claim 1 , wherein each of the plurality of fan-out portions further comprises an insulating layer disposed between the third conductive layer and the first conductive layer.

10. The array substrate of claim 9 , wherein:

the insulating layer is disposed between the second conductive layer and the first conductive layer; and

the second conductive layer and the third conductive layer are located at the same layer as one another and are isolated from one another.

11. An array substrate comprising:

a surface;

a plurality of signal lines disposed on the surface in a display area;

a plurality of signal pads disposed on the surface in a non-display area; and

a fan-out portion disposed on the surface in the non-display area, the fan-out portion comprising a plurality of fan-out lines connecting the plurality of signal lines to the plurality of signal pads,

wherein each of the plurality of fan-out lines comprises:

a first area comprising a pattern electrically connected to a corresponding signal pad of the plurality of signal pads;

a second area adjacent to the first area, the second area comprising a straight portion electrically connected to a corresponding signal line of the plurality of signal lines;

an electrically floating electrode overlapping a portion of the first area, the electrically floating electrode being spaced apart from the straight portion in a lateral direction; and

a first contact disposed at a boundary between the first area and the second area, the first contact electrically connecting the pattern and the straight portion,

wherein the array substrate further comprises:

a first insulating layer overlapping the electrically floating electrode, the first area, and the second area; and

bridge electrodes disposed on the first insulating layer, the first insulating layer being disposed between the bridge electrodes and the surface,

wherein, in a direction normal to the surface, the electrically floating electrode is disposed between the first insulating layer and the pattern,

wherein each bridge electrode of the bridge electrodes electrically connects a corresponding signal line of the plurality of signal lines to a corresponding straight portion of the straight portions of the plurality of fan-out lines, and

wherein a distance between the first contact and the corresponding signal pad reduces with increasing distance from a center portion of the fan-out portion.

12. The array substrate of claim 11 , wherein:

the pattern comprises a first conductive layer; and

the straight portion comprises the first conductive layer and a second conductive layer disposed on the first conductive layer.

13. The array substrate of claim 12 , further comprising:

a second insulating layer disposed between the first conductive layer and the second conductive layer,

wherein the first contact connects a first end of the second conductive layer to the first conductive layer, and

wherein each of the plurality of fan-out lines further comprises a second contact connecting a second end of the second conductive layer to the first conductive layer.

14. The array substrate of claim 13 , wherein each of the second contacts is disposed along a same imaginary line.

15. The array substrate of claim 12 , wherein resistances of the patterns reduce from the center portion of the fan-out portion toward edges of the fan-out portion.

16. The array substrate of claim 12 , wherein lengths of the straight portions increase from the center portion toward edges of the fan-out portion.

17. The array substrate of claim 12 , wherein:

the plurality of fan-out lines are spaced from one another at gradually reducing intervals in a first region;

the plurality of fan-out lines are spaced from one another at a constant interval in a second region;

the straight portion is disposed in the first region; and

the pattern is disposed in the second region.

18. The array substrate of claim 12 , wherein:

the plurality of signal lines comprise:

a plurality of gate lines extending in a first direction; and

a plurality of data lines extending in a second direction crossing the first direction;

the first conductive layer is disposed at a same layer as the plurality of gate lines; and

the second conductive layer is disposed at a same layer as the plurality of data lines.

19. The array substrate of claim 12 , wherein each of the plurality of fan-out portions further comprises a second insulating layer disposed between the electrically floating electrode and the first conductive layer.

20. The array substrate of claim 19 , wherein:

the second insulating layer is disposed between the second conductive layer and the first conductive layer; and

the second conductive layer and the electrically floating electrode are disposed at a same layer as one another and are isolated from one another.