IP Library Granted Patent US 9,935,538
Granted Patent B2
US 9,935,538 · App. 15/077,280 · Granted Apr 3, 2018

Power factor correction circuit and driving method thereof

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Quick Facts
Patent No.
US 9,935,538
App. No.
15/077,280
Granted
Apr 3, 2018
Kind
B2
Abstract

A power factor correction circuit corrects a filter current flowing through a filter capacitor asymmetrically based on a peak of an input voltage by controlling a switching operation of a power switch, thereby correcting distortion of an input current.

Claims (45)

1. A power factor correction circuit comprising:

a filter capacitor; and

a primary side winding connected to the filter capacitor;

a power switch connected to the primary side winding to convert an input voltage into a secondary side output;

an adjustment signal generator to generate an adjustment signal based on an input detection voltage corresponding to a full-wave waveform of an input voltage to the power factor correction circuit, wherein the adjustment signal is asymmetric with respect to a peak of the full-wave waveform of the input voltage; and

a duty generator to control a switching operation of the power switch to correct a filter current flowing through the filter capacitor utilizing the adjustment signal,

wherein the adjustment signal generator comprises:

a reference signal generator to generate an adjustment reference signal synchronized with the input voltage; and

a multiplier to generate the adjustment signal by multiplying an input peak voltage corresponding to the peak of the full-wave waveform of the input voltage by the adjustment reference signal,

wherein the adjustment reference signal has a waveform for correcting distortion of an input current by the filter current.

2. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate an error voltage by correcting a difference between a voltage corresponding to an output voltage and a predetermined reference voltage, and generate a feedback signal by adding the adjustment signal to the error voltage.

3. The power factor correction circuit according to claim 2 , wherein the duty generator is to generate a sawtooth wave signal increasing with a predetermined slope in synchronization with a switching cycle of the power switch and turn off the power switch at a time point in which the sawtooth wave signal reaches the feedback signal.

4. The power factor correction circuit according to claim 1 , wherein the duty generator is synchronized with a switching cycle of the power switch and is to generate a sawtooth wave signal increasing with the controlled slope by controlling variation in slope in a direction reverse to a variation direction of the adjustment signal.

5. The power factor correction circuit according to claim 1 , wherein the duty generator is synchronized with the switching cycle of the power switch and is to generate a sawtooth wave signal increasing with a controlled beginning level by controlling variation in the beginning level in a direction reverse to a variation direction of the adjustment signal.

6. The power factor correction circuit according to claim 1 , wherein the duty generator is to determine a compensation period based on the adjustment signal and control an on-period of the power switch corresponding to the compensation period.

7. The power factor correction circuit according to claim 6 , wherein the duty generator is to calculate the compensation period by dividing a value, obtained by multiplying the adjustment signal by the switching cycle of the power switch, by a value obtained by multiplying the input voltage by the on-period of the power switch.

8. The power factor correction circuit according to claim 7 , wherein the duty generator is to generate a compensation control output by delaying a control output, based on a result of comparison between the feedback signal corresponding to the output voltage and a sawtooth wave signal, by a period corresponding to the sum of at least one switching cycle and the compensation period.

9. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate the feedback signal by controlling a reference voltage according to the adjustment signal and control a switching operation of the power switch based on a result of comparison between a sensing voltage corresponding to a current flowing through the power switch and the feedback signal.

10. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate a compensation sensing voltage by controlling variation in slope of a sensing voltage in a direction reverse to a variation direction of the adjustment signal, and control a switching operation of the power switch based on a result of comparison between the compensation sensing voltage and a reference voltage,

wherein the sensing voltage is a voltage corresponding to a current flowing through the power switch.

11. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate a compensation sensing voltage by controlling variation in a beginning level of the sensing voltage in a direction reverse to a variation direction of the adjustment signal, and control a switching operation of the power switch based on a result of comparison between the compensation sensing voltage and a reference voltage,

wherein the sensing voltage is a voltage corresponding to a current flowing through the power switch.

12. The power factor correction circuit according to claim 1 , wherein the duty generator is to generate a feedback signal based on a result of multiplication of the sum of a reference voltage and the adjustment signal by the switching cycle of the power switch, generate a sensing voltage based on the total amount of a switch current for one switching cycle of the power switch, and turn off the power switch based on a result of comparison between the sensing voltage and the feedback signal.

13. A power factor correction circuit comprising:

a filter capacitor;

an adjustment signal generator to generate an adjustment signal based on an input detection voltage corresponding to a full-wave waveform of an input voltage to the power factor correction circuit, wherein the adjustment signal is asymmetric with respect to a peak of the full-wave waveform of the input voltage; and

a power supply comprising a power switch electrically connected to the filter capacitor and converting an input voltage into output power using the power switch,

wherein the power factor correction circuit is to control a switching operation of the power switch to correct a filter current flowing through the filter capacitor utilizing the adjustment signal,

wherein the adjustment signal generator comprises:

a reference signal generator to generate an adjustment reference signal synchronized with the input voltage; and

a multiplier to generate the adjustment signal by multiplying an input peak voltage corresponding to the peak of the full-wave waveform of the input voltage by the adjustment reference signal,

wherein the adjustment reference signal has a waveform for correcting distortion of an input current by the filter current.

14. The power factor correction circuit according to claim 13 , further comprising

a duty generator to generate an error voltage by correcting a difference between a voltage corresponding to an output voltage and a predetermined reference voltage, and generate a feedback signal by adding the adjustment signal to the error voltage.

15. A method for driving a power factor correction circuit comprising a power supply electrically connected to a filter capacitor, the method comprising:

generating an adjustment signal based on an input detection voltage corresponding to a full-wave waveform of an input voltage of the power supply, wherein the adjustment signal is asymmetric with respect to a peak of the full-wave waveform of the input voltage; and

correcting a filter current flowing through the filter capacitor by controlling a switching operation of a power switch of the power supply utilizing the adjustment signal,

wherein generating the adjustment signal comprises: generating an adjustment reference signal synchronized with the input voltage, and multiplying an input peak voltage corresponding to the peak of the full-wave waveform of the input voltage by the adjustment reference signal to generate the adjustment signal, wherein the adjustment reference signal has a waveform for correcting distortion of an input current by the filter current.

16. The method according to claim 15 , wherein correcting the filter current comprises:

correcting at least one of feedback information and a control signal according to the adjustment signal; and

turning off the power switch according to a control output based on a result of comparison between the compensated one of the feedback information and the control signal, and the other thereof.

17. The method according to claim 15 , wherein correcting the filter current comprises:

generating a control output based on a result of comparison between a feedback information and a control signal;

correcting the control output according to an adjustment signal; and

turning off the power switch according the compensated control output.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2017
From: FAIRCHILD KOREA SEMICONDUCTOR, LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 044361/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2016
From: EUM, HYUN-CHUL; KIM, TAESUNG; PARK, IN-KI; KIM, YOUNG-JONG
To: FAIRCHILD KOREA SEMICONDUCTOR LTD
Reel/Frame 038412/0335 →