Passivation for a semiconductor light emitting device
View Patent ↗In embodiments of the invention, a passivation layer is disposed over a side of a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A material configured to adhere to an underfill is disposed over an etched surface of the semiconductor structure.
1. A method, comprising:
growing a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region;
etching away a portion of the p-type region and the light emitting layer to expose a portion of the n-type region;
forming an n-contact on the exposed portion of the n-type region;
forming a metal bonding layer over the n-contact;
disposing a passivation layer over an outer side of the metal bonding layer, an outer side of the n-contact, and on top of the exposed portion of the n-type region; and
disposing and underfill beneath the semiconductor structure, including over an outer side of the passivation layer, the passivation layer and the underfill forming a seal at a sidewall of the semiconductor structure.
2. The method of claim 1 further comprising attaching the semiconductor structure to a mount, wherein the underfill is disposed between the semiconductor structure and the mount.
3. The method of claim 1 wherein the passivation layer is selected from a group consisting of an insulating layer, a dielectric layer, AlN, TiN, SiO 2 , SiN x O y , SiN x , and Si 3 N 4 .
4. The method of claim 1 wherein the passivation layer is configured to reflect light emitted by the light emitting layer.
5. The method of claim 1 wherein the passivation layer is a multilayer dielectric stack.
6. A method, comprising:
forming a wafer comprising a plurality of semiconductor light emitting devices, each light emitting device comprising a light emitting layer disposed between an n-type region and a p-type region;
etching away a portion of the p-type region and the light emitting layer to expose a portion of the n-type region;
forming an n-contact on the exposed portion of the n-type region;
forming a metal bonding layer over the n-contact;
disposing a passivation layer over an outer side of the metal bonding layer, an outer side of the n-contact, on top of the exposed portion of the n-type region, and on the wafer between two semiconductor light emitting devices;
disposing an underfill beneath the wafer, including over an outer side of the passivation layer; and
cutting the wafer through the passivation layer and the underfill at a street between the two semiconductor light emitting devices to singulate the two semiconductor light emitting devices, the passivation layer and the underfill forming a seal at a sidewall of the semiconductor structure.
7. The method of claim 6 further comprising attaching the wafer to a mount, wherein the underfill is disposed between the semiconductor structure and the mount.
8. The method of claim 6 wherein the passivation layer is selected from a group consisting of an insulating layer, a dielectric layer, AlN, TiN, SiO 2 , SiN x O y , SiN x , and Si 3 N 4 .
9. The method of claim 6 wherein the passivation layer is configured to reflect light emitted by the light emitting layer.
10. A device, comprising:
a semiconductor structure comprising: a light emitting layer disposed between an n-type region and a p-type region, an n-contact on an exposed portion of the n-type region, and a metal bonding layer over the n-contact;
a passivation layer disposed on the semiconductor structure, including over an outer side of the metal bonding layer, over an outer side of the n-contact, and on top of the exposed portion of the n-type region in a street between the device and another device;
an underfill between the semiconductor structure and a mount, including over an outer side of the passivation layer; and
a sidewall where the underfill and the passivation layer forming a seal.
11. The device of claim 10 , wherein the passivation layer is configured to reflect light emitted by the light emitting layer.
12. The device of claim 10 , wherein the passivation layer is further disposed over an outer side of the exposed portion of the n-type region.
13. The device of claim 10 , wherein the passivation layer is a multilayer dielectric stack.