Ray tracing core and ray tracing chip having the same

1. A ray tracing core comprising:

a ray generation unit configured to generate an eye ray based on eye ray generation information and to generate a shading ray according to a shading ray type based on shading information, the shading information having a priority over the eye ray generation information and the eye ray generation information including a screen coordinate value;

a plurality of T&I (Traversal & Intersection) units with MIMD (Multiple Instruction stream Multiple Data stream) architecture, each of the plurality of T&I units configured to independently and concurrently process a ray with a corresponding ray type and to check whether there exists a triangle intersected with the received at least one eye ray, the triangle configuring a space in an AS (Acceleration Structure),

wherein for a ray-triangle hit point in the intersected triangle, the shading information is generated for a secondary ray according to material information in the intersected triangle or for a shadow ray for light source, and

wherein each of the plurality of T&I units includes an L1 cache and the ray tracing core includes a common L2 cache for the L1 caches in the plurality of T&I units, and when an L1 cache miss occurs in a current ray, a requirement for an L2 cache access is inputted to L1 Addr (Address) FIFO (First in First Out) and when the L2 cache access is hit, an address and data is inputted to an L1 Addr/Data (Address and Data) FIFO and otherwise, other requirement for an external memory is inputted to an L2 Addr FIFO.

2. The ray tracing core of claim 1 , further comprising:

a shading unit configured to calculate a color value about the ray-triangle hit point in the intersected triangle, the ray-triangle hit point being hit by the at least one eye ray, when there exists the triangle intersected with the at least one received eye ray.

3. The ray tracing core of claim 2 , wherein the shading unit generates shading information including a coordinate value of the ray-triangle hit point, the calculated color value and shading ray type, and wherein the shading information can further include additional information according to the shading ray type.

4. The ray tracing core of claim 3 , wherein the ray generation unit generates shading ray or stores a final color value based on the generated shading information.

5. The ray tracing core of claim 4 , further comprising:

a secondary ray stack configured to store at least one secondary ray, wherein when a number of the at least one secondary ray is equal to or greater than 2, the ray generation unit allocates one of the at least one secondary ray to one of the plurality of the T&I units and pushes other secondary ray into the secondary ray stack.

6. The ray tracing core of claim 5 , wherein when the shading ray type corresponds to null ray, the ray generation unit pops the pushed secondary ray from the secondary ray stack, and allocates the popped secondary ray into one of the plurality of the T&I units.

7. The ray tracing core of claim 1 , wherein each of the plurality of the T&I units includes a T&I pipeline unit configured to perform a traversal procedure, a triangle list fetch procedure and ray-triangle intersection test procedure based on the eye ray.

8. The ray tracing core of claim 7 , wherein each of the plurality of the T&I units further includes an input buffer and an output buffer for the MIMD architecture.

9. The ray tracing core of claim 1 , further comprising:

a setup processing unit configured to divide a screen into a plurality of blocks for increasing hit ratio of each of the plurality of the T&I units and determine eye ray generation order based on each of the plurality of the blocks.

10. The ray tracing core of claim 9 , wherein the setup processing unit divides the screen into a plurality of m×n (m and n are even) pixel blocks (hereinafter, referred to as super-blocks), divides each of the super-blocks into n (n is the number of the plurality of the blocks) pixel blocks (hereinafter, referred to as sub-blocks) and determines eye ray generation order based on each of the sub-blocks and wherein each of the sub-blocks has the same size.

11. The ray tracing core of claim 10 , wherein the setup processing unit includes a linear n-bit counter for determining the eye ray generation order, wherein a first group of the linear n-bit counter represents an x coordinate value of the sub-blocks and a second group of the linear n-bit counter represents a y coordinate value of the sub-blocks and wherein the first group may include at least one non-continuous bit and the second group may include at least one other non-continuous bit.

12. The ray tracing core of claim 1 , wherein when the L1 cache miss occurs in a current cycle, the L1 cache miss bypasses without stall so that the L1 cache miss is solved in a next cycle.

13. A ray tracing core, comprising:

a setup processing unit configured to multiplex one of eye ray generation information or shading information, the shading information having a priority over the eye ray generation information, the eye ray generation information including a screen coordinate value and the shading information including a coordinate value, a color value and shading ray type for a ray-triangle hit point;

a ray generation unit configured to generate an eye ray based on eye ray generation information and to generate a shading ray according to a shading ray type based on shading information; and

a plurality of T&I (Traversal & Intersection) units with MIMD (Multiple Instruction stream Multiple Data stream) architecture, each of the plurality of T&I units configured to independently and concurrently process a ray with a corresponding ray type and to check whether there exists a triangle intersected with the received at least one eye ray, the triangle configuring a space in an AS (Acceleration Structure),

wherein for a ray-triangle hit point in the intersected triangle, the shading information is generated for a secondary ray according to material information in the intersected triangle or for a shadow ray for light source, and

wherein each of the plurality of T&I units includes an L1 cache and the ray tracing core includes a common L2 cache for the L1 caches in the plurality of T&I units, and when an L1 cache miss occurs in a current ray, a requirement for an L2 cache access is inputted to L1 Addr (Address) FIFO (First in First Out) and when the L2 cache access is hit, an address and data is inputted to an L1 Addr/Data (Address and Data) FIFO and otherwise, other requirement for an external memory is inputted to an L2 Addr FIFO.

14. The ray tracing core of claim 13 , further comprising:

a hit point calculation unit configured to calculate the ray-triangle hit point at the intersected triangle based on the generated at least one eye ray or shading ray.

15. The ray tracing core of claim 14 , further comprising:

a shading unit configured to calculate a color value of the calculated ray-triangle hit point and transmit shading information for the calculated ray-triangle hit point.

16. The ray tracing core of claim 13 , wherein each of the plurality of T&I units includes a T&I pipeline unit configured to perform a traversal procedure, a triangle list fetch procedure and ray-triangle intersection test procedure based on the generated at least one eye ray or shading ray.

17. A ray tracing chip, comprising:

a plurality of ray tracing cores;

an XY generator configured to allocate at least one block of image to a ray tracing core of the plurality of ray tracing cores; and

a memory configured to store a final color value outputted from each of the plurality of ray tracing cores,

wherein each of the plurality of ray tracing cores comprises:

a ray generation unit configured to generate an eye ray based on eye ray generation information and to generate a shading ray according to a shading ray type based on shading information, the shading information having a priority over the eye ray generation information and the eye ray generation information including a screen coordinate value;

a plurality of T&I (Traversal & Intersection) units with MIMD (Multiple Instruction stream Multiple Data stream) architecture, each of the plurality of T&I units configured to independently and concurrently process a ray with a corresponding ray type and to check whether there exists a triangle intersected with the received at least one eye ray, the triangle configuring a space in an AS (Acceleration Structure),

wherein for a ray-triangle hit point in the intersected triangle, the shading information is generated for a secondary ray according to material information in the intersected triangle or for a shadow ray for light source, and

wherein each of the plurality of T&I units includes an L1 cache and each ray tracing core includes a common L2 cache for the L1 caches in the plurality of T&I units, and when an L1 cache miss occurs in a current ray, a requirement for an L2 cache access is inputted to L1 Addr (Address) FIFO (First in First Out) and when the L2 cache access is hit, an address and data is inputted to an L1 Addr/Data (Address and Data) FIFO and otherwise, other requirement for an external memory is inputted to an L2 Addr FIFO.

18. A ray tracing chip, comprising:

a plurality of ray tracing cores;

an XY generator configured to allocate at least one block of image to an adequate ray tracing core of the plurality of ray tracing cores; and

a memory configured to store a final color value outputted from each of the plurality of ray tracing cores,

wherein each of the plurality of ray tracing cores comprises:

a setup processing unit configured to multiplex one of eye ray generation information or shading information, the shading information having a priority over the eye ray generation information, the eye ray generation information including a screen coordinate value and the shading information including a coordinate value, a color value and shading ray type for a ray-triangle hit point;

a ray generation unit configured to generate an eye ray based on eye ray generation information and to generate a shading ray according to a shading ray type based on shading information; and

a plurality of T&I (Traversal & Intersection) units with MIMD (Multiple Instruction stream Multiple Data stream) architecture, each of the plurality of T&I units configured to independently and concurrently process a ray with a corresponding ray type and to check whether there exists a triangle intersected with the received at least one eye ray, the triangle configuring a space in an AS (Acceleration Structure),

wherein for a ray-triangle hit point in the intersected triangle, the shading information is generated for a secondary ray according to material information in the intersected triangle or for a shadow ray for light source, and

wherein each of the plurality of T&I units includes an L1 cache and each ray tracing core includes a common L2 cache for the L1 caches in the plurality of T&I units, and when an L1 cache miss occurs in a current ray, a requirement for an L2 cache access is inputted to L1 Addr (Address) FIFO (First in First Out) and when the L2 cache access is hit, an address and data is inputted to an L1 Addr/Data (Address and Data) FIFO and otherwise, other requirement for an external memory is inputted to an L2 Addr FIFO.