Artificial ripple modulation control circuitry

1. A power supply system, comprising:

power switch circuitry configured to switch an input voltage of a power supply to generate a switched input voltage;

output circuitry including an inductor to generate an output voltage of the power supply from the switched input voltage;

pulse width modulation (PWM) controller circuitry configured to generate a PWM signal to control the power switch circuitry, wherein the PWM controller circuitry is further configured to turn OFF the PWM signal based on a ramp signal that emulates, at least in part, current of the inductor and a feedback signal indicative of an error between the output voltage and a reference voltage; and

inductor ripple current and slope compensation voltage emulation circuitry configured to receive a signal proportional to the input voltage of the power supply and the PWM signal and generate the ramp signal that emulates the current of the inductor.

2. The power supply system of claim 1 , wherein the PWM controller circuitry comprises:

amplifier circuitry configured to generate the feedback signal based on the error between the output voltage of the power supply and the reference voltage;

pulse width modulation (PWM) logic circuitry configured to compare the ramp signal and the feedback signal to determine a timing to turn the PWM signal OFF; and

reset circuitry configured to reset the ramp signal to a predetermined value that is less than the feedback signal when the PWM signal is turned OFF.

3. The power supply system of claim 2 , wherein the inductor ripple current and slope compensation circuitry generates the ramp signal starting at approximately a leading edge of the PWM signal and having a slope based on the signal proportional to the input voltage of the power supply.

4. The power supply of claim 1 , wherein the reference signal is a signal indicative of, or proportional to, an output voltage target value.

5. The power supply of claim 1 , wherein the PWM circuitry comprises:

comparator circuitry configured to compare the ramp signal and the feedback signal and generate an output signal; and

flip-flop circuitry configured to receive the output signal and generate the PWM signal, wherein the output signal resets the flip-flop circuitry when the ramp signal is equal to or greater than the feedback signal to turn the PWM signal OFF.

6. The power supply of claim 5 , wherein the PWM circuitry further comprises:

a first current source configured to generate a current proportional to the output voltage of the power supply; and

a first resistor coupled to the first current source, wherein the feedback signal is represented by a voltage drop across the first resistor.

7. The power supply of claim 6 , wherein the PWM circuitry further comprises:

a second current source configured to generate a current proportional to the input voltage of the power supply;

a second resistor controllably coupled to the second current source; and

a reset capacitor controllably coupled to the second current source,

wherein the ramp signal is generated when the second current source is coupled to the second resistor and the reset capacitor, as controlled by a leading edge of the PWM signal, and wherein the reset capacitor and the second resistor are decoupled from the second current source when the PWM signal is OFF.

8. The power supply of claim 7 , wherein the PWM circuitry further comprises:

pulse circuitry controllably coupled to the second resistor and the reset capacitor, wherein the pulse circuitry is configured to generate a pulse signal to reset a charge on the reset capacitor.

9. The power supply of claim 8 , wherein the PWM circuitry further comprises:

buffer circuitry configured to controllably couple the first current source to the reset capacitor based on the pulse signal.

10. Pulse width modulation (PWM) controller circuitry, comprising:

inductor current and slope compensation voltage emulation circuitry configured to receive a voltage proportional to an input voltage of a power supply and a pulse width modulation (PWM) signal and generate a ramp signal indicative of, or proportional to, inductor current of an inductor associated with the power supply and a slope compensation signal of an output voltage of the power supply;

amplifier circuitry configured to generate a feedback signal based on an error between the output voltage of the power supply and a reference signal;

PWM logic circuitry configured to generate the PWM signal, the PWM logic circuitry further configured to compare the ramp signal and the feedback signal to determine a timing to turn the PWM signal OFF; and

reset circuitry configured to reset the ramp signal to a predetermined value that is less than the feedback signal when the PWM signal is turned OFF.

11. The PWM controller circuitry of claim 10 , wherein the inductor current and slope compensation circuitry generates the ramp signal starting at approximately a leading edge of the PWM signal and having a slope based on the voltage proportional to the input voltage of the power supply.

12. The PWM controller circuitry of claim 10 , wherein the reference signal is a signal indicative of, or proportional to, an output voltage target value.

13. The PWM controller circuitry of claim 10 , wherein the PWM circuitry comprises:

comparator circuitry configured to compare the ramp signal and the feedback signal and generate an output signal; and

flip-flop circuitry configured to receive the output signal and generate the PWM signal, wherein the output signal resets the flip-flop circuitry when the ramp signal is equal to or greater than the feedback signal to turn the PWM signal OFF.

14. The PWM controller circuitry of claim 13 , wherein the PWM circuitry further comprises:

a first current source configured to generate a current proportional to the output voltage of the power supply; and

a first resistor coupled to the first current source, wherein the feedback signal is represented by a voltage drop across the first resistor.

15. The PWM controller circuitry of claim 14 , wherein the PWM circuitry further comprises:

a second current source configured to generate a current proportional to the input voltage of the power supply;

a second resistor controllably coupled to the second current source; and

a reset capacitor controllably coupled to the second current source,

wherein the ramp signal is generated when the second current source is coupled to the second resistor and the reset capacitor, as controlled by a leading edge of the PWM signal, and wherein the reset capacitor and the second resistor are decoupled from the second current source when the PWM signal is OFF.

16. The PWM controller circuitry of claim 15 , wherein the PWM circuitry further comprises:

pulse circuitry controllably coupled to the second resistor and the reset capacitor, wherein the pulse circuitry is configured to generate the pulse signal to reset a charge on the reset capacitor.

17. The PWM controller circuitry of claim 16 , wherein the PWM circuitry further comprises:

buffer circuitry configured to controllably couple the first current source to the reset capacitor based on the pulse signal.

18. A method, comprising:

turning a pulse width modulation (PWM) signal ON to control a switch of a power supply;

generating a ramp signal, based on the PWM signal and an input voltage to the power supply, that emulates, at least in part, inductor current of the power supply;

generating a feedback signal proportional to an error between an output voltage and a reference signal;

comparing the ramp signal and the feedback signal; and

turning the PWM signal OFF when the ramp signal is approximately equal to the feedback signal.

19. The method of claim 18 , further comprising:

resetting the ramp signal to a predetermined value that is less than the feedback signal.