IP Library Granted Patent US 9,500,804
Granted Patent B2
US 9,500,804 · App. 15/080,476 · Granted Nov 22, 2016

Silicon photonics device and communication system therefor

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Quick Facts
Patent No.
US 9,500,804
App. No.
15/080,476
Granted
Nov 22, 2016
Kind
B2
Abstract

A silicon photonics device and system therefor. The silicon photonics device can include a 300 nm SOI (silicon-on-insulator with 300 nm top Si) overlying a substrate member. A waveguide structure can be configured from a portion of the SOI layer and disposed overlying the substrate member. This waveguide structure can include an AWG (Arrayed Waveguide Gratings) structure with 300 nm×300 nm symmetric grating waveguides or an Echelle grating structure characterized by a top silicon thickness of 300 nm. The waveguide structure can also include an index compensator material configured to provide at least two material index ratings in the waveguide structure.

Claims (25)

1. A system comprising a silicon photonics device, the system comprising:

a silicon photonics device comprising:

a substrate member;

a PBS (Polarization Beam Splitter) overlying the substrate member, the PBS having a TE+TM (Transverse Electric+Transverse Magnetic) input and a TE output and a TM output;

a TE optimized demux (demultiplexer) overlying the substrate member, the TE optimized demux having a TE demux input coupled to the TE output, the TE optimized demux having a plurality of TE demux outputs;

a TM optimized demux overlying the substrate member, the TM optimized demux having a TM demux input coupled to the TM output, the TM optimized demux having a plurality of TM demux outputs; and

a plurality of PD (photodiode) structures overlying the substrate, each of the PD structures being coupled to one of the plurality of TE demux outputs by a TE-PD path and one of the plurality of TM demux outputs by a TM-PD path; and

wherein the TE optimized demux and the TM optimized demux comprises a waveguide structure selected from a group consisting of: an AWG (Arrayed Waveguide Gratings) structure with 300 nm×300 nm grating waveguides, an Echelle gratings structure with 300 nm top silicon thickness; and

an interface coupled to the silicon photonics device.

2. The system of claim 1 wherein the TE-PD path coupled to each of the PD structures and the TM-PD path coupled to each of the PD structures are configured to be substantially time delay compensated using delay lines.

3. The system of claim 1 wherein for each PD structure the TE-PD path and the TM-PD path are coupled on opposite sides of the PD structure or coupled on the same side of the PD structure with an offset from the center.

4. The system of claim 1 wherein each PD structure comprises a first PD electrically coupled to a second PD, and wherein the TE-PD path is coupled to the first PD and the TM-PD path is coupled to the second PD.

5. The system of claim 1 wherein each of the plurality of PD structures comprises a PBC (Polarization Beam Combiner) having a PBC output coupled to a PD, and wherein the PBC comprises a PBC TE input coupled to one of the plurality of TE demux outputs and a PBC TM input coupled to one of the plurality of TM demux outputs.

6. The system of claim 1 wherein the waveguide structure comprises an index compensator material selected from a group consisting of: SiO2, Si3N4, SiOxNy, air, index matching fluid/oil/epoxy/glue or SiNx as a cladding material.

7. A system comprising a silicon photonics device, the system comprising:

a silicon photonics device comprising:

a substrate member;

a PBS (Polarization Beam Splitter) overlying the substrate member, the PBS having a TE+TM (Transverse Electric +Transverse Magnetic) input and a TE output and a TM output;

a polarization dependent demux (demultiplexer) overlying the substrate member, the polarization dependent demux having a TE demux input coupled to the TE output and a TM demux input coupled to the TM output, the polarization dependent demux having a plurality of TE+TM demux outputs; and

a plurality of PD (photodiode) structures overlying the substrate, each of the PD structures being coupled to one of the plurality of TE+TM demux outputs by a common delay line; and

an interface coupled to the silicon photonics device.

8. The system of claim 7 wherein the TE output comprises a TE path and the TM output comprises a TM path, and wherein the TE and TM path are configured to be substantially time delay compensated using delay lines.

9. A system comprising:

a polarization independent multiplexer/demultiplexer device comprising a waveguide characterized by a repeating feature of an AWG/Echelle grating configured such that a TE light input and a TM light input focus to the waveguide, wherein the TE light and the TM light are characterized by different grating orders; and

an interface coupled to the polarization independent multiplexer/demultiplexer device.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2017
From: KATO, MASAKI; NAGARAJAN, RADHA
To: INPHI CORPORATION
Reel/Frame 041933/0135 →