IP Library Granted Patent US 9,697,903
Granted Patent B1
US 9,697,903 · App. 15/081,306 · Granted Jul 4, 2017

Nonvolatile memory device and data storage device including the same

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Quick Facts
Patent No.
US 9,697,903
App. No.
15/081,306
Granted
Jul 4, 2017
Kind
B1
Abstract

A data storage device includes a nonvolatile memory device; and a controller suitable for providing a normal erase command or a fine erase command to the nonvolatile memory device, wherein the nonvolatile memory device performs a first normal erase loop in which a first normal erase voltage and an erase verify voltage are applied to erase target memory cells, according to the normal erase command, and performs a first fine erase loop in which a first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, according to the fine erase command.

Claims (19)

1. A data storage device comprising:

a nonvolatile memory device; and

a controller coupled to the nonvolatile memory device, the controller being suitable for providing a normal erase command or a fine erase command to the nonvolatile memory device;

wherein the nonvolatile memory device is suitable for performing a first normal erase loop and a first fine erase loop according to the normal and fine erase commands, respectively,

wherein the first normal erase loop comprises applying a first normal erase voltage and an erase verify voltage to erase target memory cells selected according to the normal erase command, and the first fine erase loop comprises applying a first fine erase voltage and an erase verify voltage to the erase target memory cells,

wherein, when it is determined that the erase target memory cells are not erased by the first normal erase loop, the nonvolatile memory device performs a second normal erase loop in which a second normal erase voltage increased by a first increment from the first normal erase voltage and the erase verify voltage are applied to the erase target memory cells,

wherein, when it is determined that the erase target memory cells are not erased by the first fine erase loop, the nonvolatile memory device performs a second fine erase loop in which a second fine erase voltage increased by a second increment from the first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, and

wherein a magnitude of the first increment between the normal erase loops is larger than a magnitude of the second increment between the fine erase loops.

2. The data storage device according to claim 1 , wherein a level of the first normal erase voltage is higher than a level of the first fine erase voltage.

3. The data storage device according to claim 1 , wherein the controller provides the fine erase command to the nonvolatile memory device, while operating in a background mode in which there is no access request from an external device.

4. The data storage device according to claim 1 , wherein the controller provides the normal erase command or the fine erase command to the nonvolatile memory device, while operating in a normal mode in which there is an access request from the external device.

5. A nonvolatile memory device comprising:

memory cells;

a voltage generator suitable for generating voltages to be provided to the memory cells; and

a control logic suitable for performing a first normal erase loop in which the voltage generator is controlled so that a first normal erase voltage and an erase verify voltage are applied to erase target memory cells among the memory cells, according to a normal erase command provided from an external device, and performing a first fine erase loop in which the voltage generator is controlled so that a first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, according to a fine erase command provided from the external device,

wherein, when it is determined that the erase target memory cells are not erased by the first normal erase loop, the control logic performs a second normal erase loop in which the voltage generator is controlled so that a second normal erase voltage increased by a first increment from the first normal erase voltage and the erase verify voltage are applied to the erase target memory cells,

wherein, when it is determined that the erase target memory cells are not erased by the first fine erase loop, the control logic performs a second fine erase loop in which the voltage generator is controlled so that a second fine erase voltage increased by a second increment from the first fine erase voltage and the erase verify voltage are applied to the erase target memory cells, and

wherein a magnitude of the first increment between the normal erase loops is larger than a magnitude of the second increment between the fine erase loops.

6. The nonvolatile memory device according to claim 5 , wherein a level of the first normal erase voltage is higher than a level of the first fine erase voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 25, 2016
From: UM, GI PYO
To: SK HYNIX INC.
Reel/Frame 038262/0556 →