Sensor bus communication system

1. An apparatus comprising:

a first circuitry comprising a first input/output (IO) interface;

a second circuitry comprising a second input/output (IO) interface; and

a datapath circuitry coupled to the first circuitry and the second circuitry,

wherein the second circuitry is to convert a transaction received on the second IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the second IO interface; and

wherein the first IO interface comprises a serial data bus which is operable at a first frequency, and the second IO interface comprises a serial data bus which is operable at a second frequency, the first frequency being greater than the second frequency;

wherein the second circuitry is to write a first transaction received to a buffer at the first frequency, and is to retrieve the first transaction from the buffer at the second frequency; and

wherein the second circuitry is to write a second transaction received to a buffer at the second frequency, and is to retrieve the second transaction from the buffer at the first frequency.

2. The apparatus of claim 1 , wherein the second IO interface comprises an Inter Integrated Circuit (I2C) interface.

3. The apparatus of claim 1 , comprising:

a third circuitry comprising a third input/output (IO) interface,

wherein the third circuitry is to convert a transaction received on the third IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the third IO interface.

4. The apparatus of claim 3 , wherein the third IO interface is one of: a Serial Peripheral Interface (SPI) bus, a UART (Universal Asynchronous Receiver/Transmitter) bus, or a debug bus.

5. The apparatus of claim 3 ,

wherein the datapath circuitry is to forward a transaction received on the second IO interface to the first circuitry, and is to forward a transaction received on the third IO interface to the first circuitry; and

wherein the datapath circuitry is to arbitrate between a transaction received on the second IO interface and a transaction received on the third IO interface.

6. The apparatus of claim 1 , comprising an oscillator.

7. The apparatus of claim 1 , wherein the first IO interface is operable at a first high-voltage level, and the second IO interface is operable at a second high-voltage level greater than the first high-voltage level.

8. The apparatus of claim 7 ,

wherein the second circuitry has a first part operable at the first frequency and at the first high-voltage level, and has a second part operable at the second frequency and at the second high-voltage level; and

wherein the first part is driven by a first clock source and a first supply voltage, and the second part is driven by a second clock source separate from the first clock source and a second supply voltage separate from the first supply voltage.

9. The apparatus of claim 1 ,

wherein the second circuitry is to map one or more fields of a first transaction compliant with the first IO interface into one or more fields for a transaction compliant with the second IO interface; and

wherein the second circuitry is to map one or more fields of a second transaction compliant with the second IO interface into one or more fields for a transaction compliant with the first IO interface.

10. An apparatus comprising:

a host-protocol transceiver coupled to a host-protocol input/output (IO) interface comprising a serial data bus;

a first guest-protocol transceiver coupled to a first guest-protocol input/output (IO) interface comprising a serial data bus; and

a second guest-protocol transceiver coupled to a second guest-protocol input/output (IO) interface,

wherein the serial data bus of the host-protocol IO interface is operable at a first frequency, and the serial data bus of the first guest-protocol IO interface is operable at a second frequency, the first frequency being greater than the second frequency; and

wherein the host-protocol IO interface is operable at a first high-voltage level, and the first guest-protocol IO interface is operable at a second high-voltage level, the second high-voltage level being greater than the first high-voltage level.

11. The apparatus of claim 10 , wherein the first guest-protocol IO interface comprises an Inter Integrated Circuit (I2C) interface.

12. The apparatus of claim 10 , wherein the second guest-protocol IO interface is one of: a Serial Peripheral Interface (SPI) interface, a Universal Asynchronous Receiver/Transmitter (UART) interface, or a Debug Bus interface.

13. The apparatus of claim 10 , comprising:

a first guest-protocol conversion circuitry to convert a transaction received by the first guest-protocol transceiver into a first converted transaction for the host-protocol transceiver, and to convert a transaction received by the host-protocol transceiver into a transaction for the first guest-protocol transceiver; and

a second guest-protocol conversion circuitry to convert a transaction received by the second guest-protocol transceiver into a second converted transaction for the host-protocol transceiver, and to convert a transaction received by the host-protocol transceiver into a transaction for the second guest-protocol transceiver.

14. The apparatus of claim 13 , comprising:

a first datapath circuitry to forward the first converted transaction for the host-protocol transceiver to the host-protocol transceiver; and

a second datapath circuitry to forward the second converted transaction for the host-protocol transceiver to the host-protocol transceiver.

15. The apparatus of claim 14 , comprising:

a bus selection circuitry to select between the first datapath circuitry and the second datapath circuitry based upon an assigned priority of the first guest-protocol IO interface and an assigned priority of the second guest-protocol IO interface.

16. The apparatus of 13 ,

wherein the first guest-protocol conversion circuitry is to buffer a first transaction received at the first frequency, and is to retrieve the first transaction at the second frequency; and

wherein the first guest-protocol conversion circuitry is to buffer a second transaction received at the second frequency, and is to receive the second transaction at the second frequency.

17. The apparatus of claim 13 ,

wherein the first guest-protocol conversion circuitry is to map one or more fields of a first transaction compliant with the host-protocol IO interface into one or more fields for a transaction compliant with the first guest-protocol IO interface; and

wherein the first guest-protocol conversion circuitry is to map one or more fields of a second transaction compliant with the first guest-protocol IO interface into one or more fields for a transaction compliant with the host-protocol IO interface.

18. The apparatus of claim 10 , comprising

a first guest-protocol conversion circuitry to convert a transaction received by the first guest-protocol transceiver into a transaction for the host-protocol transceiver, and to convert a transaction received by the host-protocol transceiver into a transaction for the first guest-protocol transceiver,

wherein the first guest-protocol conversion circuitry has a first part operable at the first frequency and at the first high-voltage level, and has a second part operable at the second frequency and at the second high-voltage level; and

wherein the first part is driven by a first clock source and a first supply voltage, and the second part is driven by a second clock source separate from the first clock source and a second supply voltage separate from the first supply voltage.

19. The apparatus of claim 10 , wherein the host-protocol IO interface comprises a serial clock line and a serial data line.

20. A system comprising a memory, a processor coupled to the memory, and a wireless interface to allow the processor to communicate with another device, the processor and a repeater including:

a first circuitry comprising a first input/output (IO) interface;

a second circuitry comprising a second input/output (IO) interface; and

a datapath circuitry coupled to the first circuitry and the second circuitry,

wherein the second circuitry is to convert a transaction received on the second IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the second IO interface; and

wherein the first IO interface comprises a serial data bus which is operable at a first frequency, and the second IO interface comprises a serial data bus which is operable at a second frequency, the first frequency being greater than the second frequency;

wherein the second circuitry is to map one or more fields of a first transaction compliant with the first IO interface into one or more fields for a transaction compliant with the second IO interface; and

wherein the second circuitry is to map one or more fields of a second transaction compliant with the second IO interface into one or more fields for a transaction compliant with the first IO interface.

21. The system of claim 20 , comprising:

a third circuitry comprising a third input/output (IO) interface,

wherein the third circuitry is to convert a transaction received on the third IO interface into a transaction for the first IO interface, and to convert a transaction received on the first IO interface into a transaction for the third IO interface.

22. The system of claim 20 ,

wherein the datapath circuitry is to forward a transaction received on the second IO interface to the first circuitry, and is to forward a transaction received on the third IO interface to the first circuitry; and

wherein the datapath circuitry is to arbitrate between a transaction received on the second IO interface and a transaction received on the third IO interface.

23. The system of claim 20 , wherein the second IO interface comprises an Inter Integrated Circuit (I2C) interface.