Alternative direct-mapped cache and cache replacement method

1. A method, comprising:

storing a first block of main memory in a cache line of a direct-mapped cache;

storing a first tag in a current tag field of the cache line, wherein the first tag identifies a first memory address for the first block of main memory, and

storing a second tag in a previous miss tag field of the cache line in response to receiving a memory reference having a tag that does not match the tag stored in the current tag field, wherein the second tag identifies a second memory address for a second block of main memory, and wherein the first and second blocks of main memory are both mapped to the cache line.

2. The method of claim 1 , wherein the first block of main memory is stored in the cache line in response to receiving a memory reference to the first block while the cache line does not have a block stored in the cache line, and wherein the first tag is stored in the current tag field of the cache line in response to storing the first block of main memory in the cache line.

3. The method of claim 1 , further comprising:

storing a first binary value in a last reference bit field in the cache line of the direct-mapped cache, wherein the first binary value indicates that the most recently received memory reference was directed to the tag stored in the current tag field.

4. The method of claim 1 , further comprising:

storing a binary value in a last reference bit field in the cache line of the direct-mapped cache, wherein the last reference bit indicates whether the most recently received memory reference was directed to the tag stored in the current tag field or the tag stored in the previous miss tag field.

5. The method of claim 4 , further comprising:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the previous miss tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the previous miss tag field, replacing the first block of main memory stored in the cache line with the second block of main memory and replacing the first tag in the current tag field with the second tag.

6. The method of claim 5 , further comprising:

writing the first block back to main memory prior to replacing the first block of main memory with the second block of main memory in response to the first block having been modified since the first block was written back to main memory.

7. The method of claim 4 , further comprising:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the current tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the previous miss tag field, maintaining the first block of main memory stored in the cache line, maintaining the first tag in the current tag field, and changing the binary value stored in the last reference bit field to indicate that the most recent memory reference was directed to the tag stored in the current tag field.

8. The method of claim 4 , further comprising:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the previous miss tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the current tag field, maintaining the first block of main memory stored in the cache line, maintaining the first tag in the current tag field, and changing the binary value stored in the last reference bit field to indicate that the most recent memory reference was directed to the tag stored in the previous miss tag field.

9. The method of claim 4 , further comprising:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the current tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the current tag field, maintaining the first block of main memory stored in the cache line, maintaining the first tag in the current tag field, and maintaining the binary value stored in the last reference bit field to indicate that the most recent memory reference was directed to the tag stored in the current tag field.

10. The method of claim 4 , further comprising:

in response to subsequently receiving a memory reference having an associated tag that does not match the tag stored in the previous miss tag field and does not match the tag stored in the current tag field, maintaining the first block of main memory stored in the cache line, maintaining the first tag in the current tag field, storing the associated tag in the previous miss tag field and causing the last reference bit to indicate that the most recent memory reference was directed to the tag stored in the previous miss tag field.

11. The method of claim 1 , wherein each cache line of the direct-mapped cache further includes a multiple reference bit indicating whether the current memory address has been referenced more than once.

12. The method of claim 1 , wherein each tag is a first portion of a main memory address that is mapped to the cache line, and wherein each memory address includes an index portion that identifies the cache line being addressed.

13. The method of claim 1 , further comprising:

performing a read operation on the block stored in the cache line in response to receiving a read instruction with a memory reference having a tag that matches the tag stored in the current tag field; and

performing a write operation on the block stored in the cache line in response to receiving a write instruction with a memory reference having a tag that matches the tag stored in the current tag field.

14. A computer program product for implementing a cache replacement policy, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

store a first block of main memory in a cache line of a direct-mapped cache;

store a first tag in a current tag field of the cache line, wherein the first tag identifies a first memory address for the first block of main memory, and

store a second tag in a previous miss tag field of the cache line in response to receiving a memory reference having a tag that does not match the tag stored in the current tag field, wherein the second tag identifies a second memory address for a second block of main memory, and wherein the first and second blocks of main memory are both mapped to the cache line.

15. The computer program product of claim 14 , wherein the program instructions are further executable by the processor to cause the processor to:

store a binary value in a last reference bit field in the cache line of the direct-mapped cache, wherein the last reference bit indicates whether the most recently received memory reference was directed to the tag stored in the current tag field or the tag stored in the previous miss tag field.

16. The computer program product of claim 15 , wherein the program instructions are further executable by the processor to cause the processor to:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the previous miss tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the previous miss tag field, replace the first block of main memory stored in the cache line with the second block of main memory and replace the first tag in the current tag field with the second tag.

17. The computer program product of claim 15 , wherein the program instructions are further executable by the processor to cause the processor to:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the current tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the previous miss tag field, maintain the first block of main memory stored in the cache line, maintain the first tag in the current tag field, and change the binary value stored in the last reference bit field to indicate that the most recent memory reference was directed to the tag stored in the current tag field.

18. The computer program product of claim 15 , wherein the program instructions are further executable by the processor to cause the processor to:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the previous miss tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the current tag field, maintain the first block of main memory stored in the cache line, maintain the first tag in the current tag field, and change the binary value stored in the last reference bit field to indicate that the most recent memory reference was directed to the tag stored in the previous miss tag field.

19. The computer program product of claim 15 , wherein the program instructions are further executable by the processor to cause the processor to:

in response to subsequently receiving a memory reference having a tag that matches the tag stored in the current tag field and the binary value stored in the last reference bit field indicating that the most recent memory reference was directed to the tag stored in the current tag field, maintain the first block of main memory stored in the cache line, maintain the first tag in the current tag field, and maintain the binary value stored in the last reference bit field to indicate that the most recent memory reference was directed to the tag stored in the current tag field.

20. The computer program product of claim 15 , wherein the program instructions are further executable by the processor to cause the processor to:

in response to subsequently receiving a memory reference having an associated tag that does not match the tag stored in the previous miss tag field and does not match the tag stored in the current tag field, maintain the first block of main memory stored in the cache line, maintain the first tag in the current tag field, store the associated tag in the previous miss tag field and cause the last reference bit to indicate that the most recent memory reference was directed to the tag stored in the previous miss tag field.