High-performance device for protection from electrostatic discharge

1. A semiconductor device for protection from electrostatic discharge, the semiconductor device comprising:

a plurality of modules for protection from electrostatic discharge, each module of the plurality of modules comprising:

a thyristor having terminals and a gate, and

a diode coupled in antiparallel to the terminals of the thyristor, wherein each module of the plurality of modules is sized to share a saturation current with neighboring modules of the plurality of modules when an electrostatic discharge current is received;

a resistive network coupling the plurality of modules between two terminals;

a triggering circuit comprising a common triggering output, wherein the common triggering output is coupled to the gate of the thyristor of each module of the plurality of modules; and

a common buried semiconductor layer contacting each module of the plurality of modules.

2. The semiconductor device according to claim 1 , wherein each module of the plurality of modules has a concentric structure comprising two blocks having respectively opposite types of conductivity and the common buried semiconductor layer contacts the two blocks of each module of the plurality of modules.

3. The semiconductor device according to claim 1 , wherein the plurality of modules are arranged as a matrix network.

4. The semiconductor device according to claim 1 , wherein the thyristor of each module of the plurality of modules comprises:

a first semiconductor block having a first conductivity type, the first semiconductor block being on and in physical contact with the common buried semiconductor layer;

a second semiconductor block having a second conductivity type, the second semiconductor block being on and in physical contact with the common buried semiconductor layer;

a first highly doped semiconductor region disposed in the second semiconductor block and having the second conductivity type, wherein the gate of the thyristor comprises the first highly doped semiconductor region;

a second highly doped semiconductor region disposed in the second semiconductor block and having the first conductivity type, wherein a first terminal of the terminals of the thyristor comprises the second highly doped semiconductor region;

a third highly doped semiconductor region disposed in the first semiconductor block and having the second conductivity type, wherein a second terminal of the terminals of the thyristor comprises the third highly doped semiconductor region;

a first isolation region disposed in the second semiconductor block between the first highly doped semiconductor region and the second highly doped semiconductor region; and

a second isolation region disposed in the first semiconductor block and the second semiconductor block between the second highly doped semiconductor region and the third highly doped semiconductor region.

5. The semiconductor device according to claim 1 , wherein the plurality of modules are interconnected in a daisy chain fashion.

6. The semiconductor device according to claim 1 , wherein the triggering circuit comprises a field effect transistor (FET).

7. The semiconductor device according to claim 6 , wherein the field effect transistor is an n-type FET having a gate and source terminal coupled to a second voltage terminal of the two terminals and having a drain coupled to a first voltage terminal of the two terminals and further coupled to respective gates of the thyristor of each module of the plurality of modules.

8. An integrated circuit comprising:

a first voltage rail and a second voltage rail;

a circuit component connected between the first and second voltage rails; and

an electrostatic discharge protection device comprising:

a trigger circuit,

a plurality of modules, each module of the plurality of modules comprising a thyristor having a first terminal coupled to the first voltage rail, a second terminal coupled to the second voltage rail, and a gate coupled to the trigger circuit, wherein each module of the plurality of modules is configured to reach a saturation state and to share a saturation current with neighboring modules of the plurality of modules when an electrostatic discharge current is received, and

a common buried semiconductor layer in contact with each module of the plurality of modules.

9. The integrated circuit of claim 8 , further comprising a resistive network interconnecting respective first terminals of the thyristor of each module of the plurality of modules and the first voltage rail and interconnecting respective second terminals of the thyristor of each module of the plurality of modules and the second voltage rail.

10. The integrated circuit of claim 8 , wherein the trigger circuit comprises a field effect transistor (FET).

11. The integrated circuit of claim 10 , wherein the field effect transistor is an n-type FET having a gate and source terminal coupled to the second voltage rail and having a drain coupled to the first voltage rail and further coupled to respective gates of the thyristor of each module of the plurality of modules.

12. The integrated circuit of claim 8 , wherein the plurality of modules are arranged in a matrix network.

13. The integrated circuit of claim 8 , wherein the plurality of modules are interconnected in a daisy chain fashion.

14. The integrated circuit of claim 8 , wherein the thyristor of each module of the plurality of modules comprises:

a first semiconductor block having a first conductivity type, the first semiconductor block being on and in physical contact with the common buried semiconductor layer;

a second semiconductor block having a second conductivity type, the second semiconductor block being on and in physical contact with the common buried semiconductor layer;

a first highly doped semiconductor region disposed in the second semiconductor block and having the second conductivity type, wherein the gate of the thyristor comprises the first highly doped semiconductor region;

a second highly doped semiconductor region disposed in the second semiconductor block and having the first conductivity type, wherein the first terminal of the thyristor comprises the second highly doped semiconductor region;

a third highly doped semiconductor region disposed in the first semiconductor block and having the second conductivity type, wherein the second terminal of the thyristor comprises the third highly doped semiconductor region;

a first isolation region disposed in the second semiconductor block between the first highly doped semiconductor region and the second highly doped semiconductor region; and

a second isolation region disposed in the first semiconductor block and the second semiconductor block between the second highly doped semiconductor region and the third highly doped semiconductor region.

15. A device comprising:

a common buried semiconductor layer;

a triggering device; and

a plurality of triggerable devices, each triggerable device comprising

a thyristor having a gate coupled to the triggering device, and

a diode configured in antiparallel to the thyristor, wherein

each triggerable device of the plurality of triggerable devices is in contact with the common buried semiconductor layer, and

each triggerable device of the plurality of triggerable devices is sized to reach a saturation state and to share a saturation current with neighboring triggerable devices of the plurality of triggerable devices when an electrostatic discharge current passing therethrough.

16. The device of claim 15 , further comprising a circuit to be protected from electrostatic discharge coupled across a first rail and a second rail, wherein the triggering device is coupled across the first rail and the second rail.

17. The device of claim 15 , further comprising a resistive network, wherein

each triggerable device of the plurality of triggerable devices has a first terminal and a second terminal,

respective first terminals of the plurality of triggerable devices are interconnected through the resistive network, and

respective second terminals of the plurality of triggerable devices are interconnected through the resistive network.

18. The device of claim 15 , wherein the triggerable devices are formed adjacent one another, separated from one another by isolation regions, and formed over the common buried semiconductor layer.

19. The device of claim 15 , wherein the thyristor of each triggerable device of the plurality of triggerable devices comprises:

a first semiconductor block having a first conductivity type, the first semiconductor block being on and in physical contact with the common buried semiconductor layer;

a second semiconductor block having a second conductivity type, the second semiconductor block being on and in physical contact with the common buried semiconductor layer;

a first highly doped semiconductor region disposed in the second semiconductor block and having the second conductivity type, wherein the gate of the thyristor comprises the first highly doped semiconductor region;

a second highly doped semiconductor region disposed in the second semiconductor block and having the first conductivity type, wherein a first terminal of the thyristor comprises the second highly doped semiconductor region;

a third highly doped semiconductor region disposed in the first semiconductor block and having the second conductivity type, wherein a second terminal of the thyristor comprises the third highly doped semiconductor region;

a first isolation region disposed in the second semiconductor block between the first highly doped semiconductor region and the second highly doped semiconductor region; and

a second isolation region disposed in the first semiconductor block and the second semiconductor block between the second highly doped semiconductor region and the third highly doped semiconductor region.

20. The device of claim 15 , wherein the plurality of triggerable devices are arranged in a matrix network.