Methods for data acquisition systems in real time applications
View Patent ↗A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt. SW may read system memory for this information, and handle the interrupts as required without having to query the DAQ device.
1. A peripheral device comprising:
a first register; a second register, and a third register;
control circuitry configured to:
generate an output signal, alternating between generating the output signal at least according to contents of the first register and generating the output signal at least according to contents of the second register;
copy contents of the third register into the first register when generating the output signal at least according to the contents of the second register;
copy the contents of the third register into the second register when generating the output signal at least according to the contents of the first register; and
update the contents of the third register subsequent to having copied the contents of the third register into either the first register or the second register; and
error detection circuitry configured to perform data timing error detection, wherein to perform the data timing error detection, the error detection circuitry is configured to:
receive incoming data from a host system;
detect a present first error if expected first data of the incoming data does not reach the third register in time to be available for a present sample clock period, and report the present first error to the host system upon detecting the present first error;
detect a present second error if more than the expected first data reaches the third register and is available for the present sample clock period, and report the present second error to the host system upon detecting the present second error; and
report to the host system whether expected second data of the incoming data has been received correctly for a most recent previous sample clock period.
2. The peripheral device of claim 1 , wherein in reporting to the host system whether the expected second data has been received correctly for the most recent previous sample clock period, the error detection circuitry is configured to:
report a previous first error if the expected second data did not reach the third register in time to be available for the most recent previous sample clock period; and
report a previous second error if more than the expected second data reached the third register and was available for the most recent previous sample clock period.
3. The peripheral device of claim 1 , wherein the error detection circuitry is configured to:
receive acknowledgment for the reported present first error from the host system; and
receive acknowledgment for the reported present second error from the host system.
4. The peripheral device of claim 3 , wherein the error detection circuitry is configured to:
retain an indication of the present first error at least until receiving the acknowledgment for the reported present first error; and
retain an indication of the present second error at least until receiving the acknowledgment for the reported present second error.
5. The peripheral device of claim 1 , wherein the error detection circuit is configured to perform the data timing error detection for each sample clock period of a plurality of sample clock periods that also include the present sample clock period and the most recent previous sample clock period.
6. The peripheral device of claim 1 , wherein the output signal is a periodic signal.
7. The peripheral device of claim 1 , wherein a width of each pulse of the periodic signal and a time duration between subsequent pulses of the periodic signal are defined by the contents of:
the first register when the control circuitry is generating the periodic signal at least according to the contents of the first register; and
the second register when the control circuit is generating the periodic signal at least according to the contents of the second register.
8. The peripheral device of claim 1 , wherein the control circuitry comprises a counter and wherein the output signal is an output of the counter.
9. A method for data timing error detection, the method comprising:
receiving, by a peripheral device, incoming data from a host system;
generating an output signal, alternating between generating the output signal at least according to contents of a first register and generating the output signal at least according to contents of the second register;
updating contents of a third register with the incoming data;
copying contents of the third register into the first register when generating the output signal at least according to the contents of the second register;
copying contents of the third register into the second register when generating the output signal at least according to the contents of the first register;
updating the contents of the third register subsequent to having copied the contents of the third register into either the first register or the second register;
detecting a present first error when expected first data of the incoming data does not reach the third register in time to be available for a present sample clock period, and reporting the present first error to the host system upon detecting the present first error;
detecting a present second error when more than the expected first data reaches the third register and is available for the present sample clock period, and reporting the present second error to the host system upon detecting the present second error; and
reporting to the host system whether expected second data of the incoming data has been previously correctly received for a most recent previous sample clock period.
10. The method of claim 9 , wherein said reporting whether the expected second data has been previously correctly received comprises:
reporting a previous first error if the expected second data has not reached the third register in time to be available for the most recent previous sample clock period; and
reporting a previous second error if more than the expected second data reached the third register and was available for the most recent previous sample clock period.
11. The method of claim 9 , further comprising:
receiving, by the peripheral device, acknowledgment for the reported present first error from the host system; and
receiving, by the peripheral device, acknowledgment for the reported present second error from the host system.
12. The method of claim 11 , further comprising:
retaining, by the peripheral device, an indication of the present first error at least until said receiving the acknowledgment for the reported present first error; and
retaining, by the peripheral device, an indication of the present second error at least until said receiving the acknowledgment for the reported present second error.
13. The method of claim 9 , further comprising performing said receiving, said detecting and reporting the present first error, said detecting and reporting the present second error, and said reporting whether the expected second data has been previously correctly received for each sample clock period of a plurality of sample clock periods that also include the present sample clock period and the most recent previous sample clock period.
14. A data acquisition system comprising:
a communication bus;
a host system coupled to the communication bus; and
a data acquisition device coupled to the communication bus and comprising:
a first register;
a second register;
a third register; and
control circuitry configured to:
generate an output signal, alternating between generating the output signal at least according to contents of the first register and generating the output signal at least according to contents of the second register;
copy contents of the third register into the first register when generating the output signal at least according to the contents of the second register;
copy the contents of the third register into the second register when generating the output signal at least according to the contents of the first register; and
update the contents of the third register subsequent to having copied the contents of the third register into either the first register or the second register.
15. The data acquisition system of claim 14 , wherein the control circuitry is configured to update the contents of the third register with update data received from the host system through the communication bus.
16. The data acquisition system of claim 15 , wherein the control circuitry is further configured to:
detect a present first error if the update data is not received in time to be available for a present sample clock period, and report the present first error to the host system via the communication bus upon detecting the present first error; and
detect a present second error if more than the update data reaches the third register and is available for the present sample clock period, and report the present second error to the host system via the communication bus upon detecting the present second error.
17. The data acquisition system of claim 16 , wherein the control circuitry is further configured to report to the host system via the communication bus whether previous update data for updating the contents of the third register has been received correctly for a most recent previous sample clock period.
18. The data acquisition system of claim 14 , wherein the control circuitry comprises a counter, wherein the output signal is a periodic signal output by the counter, and wherein a width of each pulse of the periodic signal and a time duration between subsequent pulses of the periodic signal are defined by the contents of:
the first register when the control circuitry is generating the periodic signal at least according to the contents of the first register; and
the second register when the control circuit is generating the periodic signal at least according to the contents of the second register.