Host to device I/O flow

1. A memory access device, comprising:

a plurality of logic circuits each configured to expose one or more virtual functions via a shared communication interface;

a memory configured to provide a plurality of I/O buffers shared across said virtual functions; and

for each of said one or more virtual functions, a corresponding submission queue comprising one or more virtual submission queue entries (SQEs);

wherein the memory access device is configured to:

receive data pushed to the memory access device by a client host system;

store the data in an allocated one of the I/O buffers;

receive a submission queue entry (SQE) that invokes one of said virtual functions with respect to the data; and

use a corresponding one of the plurality of logic circuits that is associated with the invoked virtual function to perform the virtual function with respect to the data as stored in the allocated I/O buffer.

2. The memory access device of claim 1 , wherein the device is a field programmable gate array (FPGA).

3. The memory access device of claim 2 , wherein the plurality of logic circuits are programmable blocks of the FPGA.

4. The memory access device of claim 2 , wherein the FPGA has limited memory.

5. The memory access device of claim 1 , wherein each virtual function permits one or more of the following: a read access, a pushed read access, and a write access.

6. The memory access device of claim 1 , wherein the shared communication interface is PCIe.

7. The memory access device of claim 1 , wherein the memory access device is further configured such that in the event the client host system pushes data to one of the I/O buffers, and command is pushed to an SQE.

8. The memory access device of claim 7 , wherein the memory access device is further configured to read an opcode for fetching data from an external NVM associated with the memory access device to the SQE.

9. The memory access device of claim 8 , wherein the memory access device is further configured to push the external data from one of the I/O buffers to the client host system.

10. The memory access device of claim 8 , wherein the memory access device is further configured to enqueue a completion message to a completion queue (CQ) associated with the client host system.

11. The memory access device of claim 1 , wherein the allocated I/O buffer is selected based at least in part on the invoked virtual function availability.

12. The memory access device of claim 1 , wherein the allocated SQ is selected based at least in part on the invoked virtual function availability.

13. The memory access device of claim 1 , wherein for each of said one or more virtual function, the corresponding submission queue also comprises one or more dedicated SQ.

14. The memory access device of claim 1 , further comprising a map table for mapping memory buffers exposed to a PCIe BAR 4 direct memory interface to the allocated I/O buffer.

15. The memory access device of claim 1 , wherein one client host system is allocated one virtual function such that each virtual function has a corresponding client in a plurality of supported clients.

16. The memory access device of claim 1 , wherein the corresponding submission queue comprises one or more virtual SQs in one or more of the following: 256 VFs with one queue per VF with 16 entries per queue, 256 VFs with two queues per VF with 8 entries per queue, 256 VFs with four queues per VF with 4 entries per queue, 8 VFs with 2 queues per VF with 256 entries per queue, and 4 VFs with 4 queues per VF with 256 entries per queue.

17. The memory access device of claim 1 , wherein the shared communication interface is advanced logical device interface for accessing non-volatile storage media over PCIe with SR-IOV.

18. The memory access device of claim 1 , further comprising BAR 0 MMIO access to one or more PCIe registers.

19. A method, comprising:

exposing one or more virtual functions via a shared communication interface;

providing a plurality of I/O buffers shared across said virtual functions; and

for each of said one or more virtual functions, using a corresponding submission queue comprising one or more virtual submission queue entries (SQEs);

wherein a memory access device is configured to:

receive data pushed to the memory access device by a client host system;

store the data in an allocated one of the I/O buffers;

receive a submission queue entry (SQE) that invokes one of said virtual functions with respect to the data; and

use a corresponding one of the plurality of logic circuits that is associated with the invoked virtual function to perform the virtual function with respect to the data as stored in the allocated I/O buffer.

20. A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

exposing one or more virtual functions via a shared communication interface;

providing a plurality of I/O buffers shared across said virtual functions; and

for each of said one or more virtual functions, using a corresponding submission queue comprising one or more virtual submission queue entries (SQEs);

wherein a memory access device is configured to:

receive data pushed to the memory access device by a client host system;

store the data in an allocated one of the I/O buffers;

receive a submission queue entry (SQE) that invokes one of said virtual functions with respect to the data; and

use a corresponding one of the plurality of logic circuits that is associated with the invoked virtual function to perform the virtual function with respect to the data as stored in the allocated I/O buffer.