Communication between an external processor and FPGA controller
View Patent ↗A request is received via a message submission queue. The request is sent from a core associated with an external processor coupled by a communication interface. The message submission queue is associated with a memory access engine circuit configured to perform one or more memory access functions. The memory access engine circuit is used to dequeuer a next message from its corresponding message submission queue. The memory access engine circuit is used to perform a message function invoked by the message. The memory access engine circuit is used to receive a result of performing the message function. The memory access engine circuit is used to prepare and send to an external processing core that sent the message a response message determined based at least in part on the result.
1. A memory access device, comprising:
a communication interface to an external processor comprising one or more cores, wherein the communication interface is a PCIe bus and the external processor has a lower throughput PCIe root point;
a higher throughput non-volatile memory (NVM); and
a host interface module (HIM) coupled to the communication interface and the higher throughput NVM, wherein the HIM comprises:
a lower throughput PCIe endpoint corresponding to the lower throughput PCIe root point of the external processor;
a higher throughput PCIe endpoint corresponding to the higher throughput NVM; and
a plurality of asynchronous memory access engine circuits, each configured to perform one or more memory access functions; and for each asynchronous memory access engine circuit, a corresponding message submission queue;
wherein:
said one or more cores are configured to submit requests via said corresponding message submission queues; and
each asynchronous memory access engine circuit is configured to:
dequeue a next message from its corresponding message submission queue;
perform a message function invoked by the message;
receive a result of performing the message function; and
prepare and send to an external processing core that sent the message a response message determined based at least in part on the result.
2. The memory access device recited in claim 1 , wherein the memory access device is an FPGA.
3. The memory access device recited in claim 1 , wherein the one or more memory access functions are associated with an associated set of one or more memory modules.
4. The memory access device recited in claim 3 , wherein the message function is a memory access function including one or more of the following: read, write, and push read.
5. The memory access device recited in claim 1 , wherein the message conforms to a queue-based message exchange protocol.
6. The memory access device recited in claim 5 , wherein the queue-based message exchange protocol conforms to a configuration catalog.
7. The memory access device recited in claim 6 , wherein the configuration catalog is associated with a plurality of PCI BARs (base address registers) associated with a PCI endpoint for the memory access device.
8. The memory access device recited in claim 7 , wherein a plurality of PCI BARs are associated with a plurality of multiple sets of message queues.
9. The memory access device recited in claim 1 , wherein the message includes a message identifier, an opcode, and zero or more parameters.
10. The memory access device recited in claim 9 , wherein each response message comprises the message identifier.
11. The memory access device recited in claim 1 , wherein each message submission queue is a ring buffer.
12. The memory access device recited in claim 1 , wherein an external processor core is associated with a message completion queue.
13. The memory access device recited in claim 12 , wherein each response message is sent via the message completion queue.
14. The memory access device recited in claim 13 , wherein a given response message is permitted to be sent via the message completion queue in a different order than the message was received in the message submission queue.
15. The memory access device recited in claim 13 , wherein the external processor core is associated with a return message submission queue and each asynchronous memory access engine circuit is associated with a corresponding return message completion queue.
16. The memory access device recited in claim 15 , wherein the external processor core is configured to:
dequeue a next return message from the return message submission queue;
perform a core function invoked by the return message;
receive a core result of performing the core function; and
prepare and send to an associated asynchronous memory access engine circuit a return response message determined based at least in part on the core result via the corresponding return message completion queue.
17. The memory access device recited in claim 1 , wherein each of the plurality of message submission queues differ by a priority ranking.
18. A method, comprising:
receiving a request via a message submission queue, wherein:
the request is sent from a core associated with an external processor coupled by a communication interface, wherein:
the communication interface is a PCIe bus and the external processor has a lower throughput PCIe root point;
the communication interface is coupled to a host interface module (HIM), wherein the HIM is coupled to a higher throughput non-volatile memory (NVM), and wherein the HIM comprises: a lower throughput PCIe endpoint corresponding to the lower throughput PCIe root point of the external processor; and a higher throughput PCIe endpoint corresponding to the higher throughput NVM;
and
the message submission queue is associated with an asynchronous memory access engine circuit configured to perform one or more memory access functions;
using the asynchronous memory access engine circuit to:
dequeue a next message from its corresponding message submission queue;
perform a message function invoked by the message;
receive a result of performing the message function; and
prepare and send to an external processing core that sent the message a response message determined based at least in part on the result.
19. A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
receiving a request via a message submission queue, wherein:
the request is sent from a core associated with an external processor coupled by a communication interface, wherein:
the communication interface is a PCIe bus and the external processor has a lower throughput PCIe root point;
the communication interface is coupled to a host interface module (HIM), wherein the HIM is coupled to a higher throughput non-volatile memory (NVM), and wherein the HIM comprises: a lower throughput PCIe endpoint corresponding to the lower throughput PCIe root point of the external processor; and a higher throughput PCIe endpoint corresponding to the higher throughput NVM; and
the message submission queue is associated with an asynchronous memory access engine circuit configured to perform one or more memory access functions;
dequeueing a next message from its corresponding message submission queue;
performing a message function invoked by the message;
receiving a result of performing the message function; and
preparing and send to an external processing core that sent the message a response message determined based at least in part on the result.