Semiconductor device
View Patent ↗A semiconductor device includes a first metal wiring formed on a semiconductor substrate, a first organic insulating film formed on the first metal wiring, and a second metal wiring formed to cover the first organic insulating film and having a via connected to the first metal wiring. The semiconductor device further includes a second organic insulating film formed on the first organic insulating film and having an opening to expose the second metal wiring, a bump formed on an exposed portion of the second metal wiring in the opening, and a tunnel portion formed in contact with the second metal wiring or the first organic insulating film. The tunnel portion overlaps with the second metal wiring in planar view.
1. A semiconductor device comprising:
a semiconductor substrate;
a first wiring formed on the semiconductor substrate;
a first organic insulating film formed to cover the first wiring;
a second wiring formed on the first organic insulating film and having a connection portion connected to the first wiring;
a second organic insulating film formed on the first organic insulating film to cover the second wiring and having an opening to expose the second wiring;
a bump formed on an exposed portion of the second wring in the opening; and
a tunnel portion formed in contact with the second wiring or the first organic insulating film, wherein
the tunnel portion overlaps with the second wiring in planar view.
2. The semiconductor device according to claim 1 , wherein the tunnel portion is a hollow portion or the hollow portion partially filled with an insulating film having a lower density than the first organic insulating film.
3. The semiconductor device according to claim 1 , wherein the tunnel portion is configured from a plurality of line-shaped portions.
4. The semiconductor device according to claim 1 , wherein the tunnel portion is provided in an upper portion of the first organic insulating film and disposed in contact with the second wiring.
5. The semiconductor device according to claim 1 , wherein
the tunnel portion has a first end and a second end different from the first end, and
the first end of the tunnel portion is disposed under the second wiring.
6. The semiconductor device according to claim 5 , wherein the second end of the tunnel portion is disposed in a region outside the second wiring in planar view.
7. The semiconductor device according to claim 6 , further comprising an upward tunnel portion formed in the second organic insulating film, the upward tunnel portion being connected to the second end of the tunnel portion, and extending upward from the tunnel portion.
8. The semiconductor device according to claim 1 , wherein the tunnel portion is provided under the second wiring and disposed in contact with the first organic insulating film.
9. The semiconductor device according to claim 8 , wherein the tunnel portion is provided in a lower portion of the first organic insulating film, and a top edge of the tunnel portion is covered with an inorganic insulating film.
10. The semiconductor device according to claim 8 , wherein one end of the tunnel portion is provided so as to match with an end of the second wiring in planar view.
11. The semiconductor device according to claim 8 , wherein the tunnel portion has both ends positioned inside the second wiring in planar view.
12. The semiconductor device according to claim 10 , wherein the tunnel portion is configured from a recess provided in a lower portion of the second wiring.
13. The semiconductor device according to claim 11 , further comprising an upward tunnel portion penetrating the second wiring, the upward tunnel portion being connected to the tunnel portion, and extending upward from the tunnel portion.
14. The semiconductor device according to claim 8 , wherein the tunnel portion is configured from a plurality of line-shaped portions disposed in parallel.
15. The semiconductor device according to claim 1 , wherein a width Wm of the second wiring satisfies a formula below:
Wm> 2×( a metal /a poly )× To
in which a metal represents specific gravity of a metal of the second wiring, a poly represents specific gravity of the first organic insulating film, and To represents a thickness of the first organic insulating film.
16. The semiconductor device according to claim 11 , wherein the tunnel portion is configured from a recess provided in a lower portion of the second wiring.