IP Library Granted Patent US 9,818,701
Granted Patent B2
US 9,818,701 · App. 15/089,200 · Granted Nov 14, 2017

Semiconductor device, semiconductor wafer and manufacturing method of semiconductor device

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Quick Facts
Patent No.
US 9,818,701
App. No.
15/089,200
Granted
Nov 14, 2017
Kind
B2
Abstract

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

Claims (14)

1. A semiconductor device comprising:

a semiconductor substrate having a chip region, a scribe region located at an outer periphery of said chip region, and a pad region located in said scribe region;

a seal ring located between said chip region and said scribe region, the seal ring being apart from the pad region;

a wiring layer, formed over said semiconductor substrate, including a first conductive pattern and a plurality of second conductive patterns each disposed within said pad region, said first conductive pattern being disposed along a periphery of said pad region, said second conductive patterns being disposed in an inner area of said pad region with a mutual separation, and said second conductive patterns being electrically isolated from each other;

a first insulating film formed over said wiring layer;

an uppermost wiring layer, formed over said first insulating film, including a third conductive pattern overlapped with both of said first and second conductive patterns, said third conductive pattern being electrically connected to said first conductive pattern;

a second insulating film formed over said uppermost wiring layer, wherein said third conductive pattern is exposed from said second insulating film within said pad region;

a third insulating film, formed under said wiring layer; and

a lower wiring layer, formed under said third insulating film, including a fourth conductive pattern disposed in said pad region, said second conductive patterns being electrically isolated from said first, third and fourth conductive patterns.

2. The semiconductor device as claimed in claim 1 , wherein said second conductive patterns comprise a plurality of rectangular patterns.

3. The semiconductor device as claimed in claim 1 , wherein said second conductive patterns are disposed apart inward from an edge of said semiconductor substrate.

4. The semiconductor device as claimed in claim 3 , wherein said pad region is defined by a first peripheral part opposing said edge of said semiconductor substrate, a second peripheral part reaching said edge and said first peripheral part and a third peripheral part reaching said edge and said first outer peripheral part, said first conductive pattern being disposed along said first, second, and third peripheral parts.

5. The semiconductor device as claimed in claim 1 , wherein said first and second conductive patterns are formed of a copper and said third conductive pattern is formed of aluminum.

6. The semiconductor device as claimed in claim 1 , further comprising at least a part of a monitoring device disposed in said scribe region, wherein said monitoring device is electrically connected to said third conductive pattern.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Jul 28, 2017
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 043364/0390 →