Integrated power supply for fiber optic communication devices and subsystems
View Patent ↗An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.
1. An optical assembly configured for use in fiber optic communication devices, the optical assembly comprising:
an integrated circuit (IC) mounted to a substrate, the IC being constructed using an orthogonal gate extended drain complementary metal-oxide-semiconductor (OG EDCMOS) technology, the IC including:
one or more integrated power supplies, each of the one or more power supplies including:
a filter configured to convert a source signal to an output signal of the integrated power supply, the filter including an IC passive component located in the IC and a substrate integrated passive component located in the substrate;
an active switch configured to control an entry of the source signal to the filter; and
a pulse width modulator (PWM) configured to generate a PWM output signal that triggers the active switch, wherein a first capacity of the IC passive component and a second capacity of the substrate integrated passive component are configured based on a frequency of the PWM output signal and a current of the source signal; and
other integrated components that are configured to receive the output signal from the filter and to operate based on the output signal, the other integrated components being integrated into the IC using the OG EDCMOS technology.
2. The optical assembly of claim 1 , wherein the PWM includes:
a plurality of transistors arranged between a voltage source and a ground; and
an XOR gate configured to receive one or more signals generated by cycling one or more sets of transistors of the plurality of transistors.
3. The optical assembly of claim 2 , wherein:
the one or more sets of transistors includes a first set of transistors and a second set of transistors;
the first set of transistors are configured to be cycled to generate a first clock signal;
the second set of transistors are configured to be cycled to generate a second clock signal; and
the PWM output signal includes a duty cycle which is greater than either a frequency of the first clock signal or a frequency of the second clock signal.
4. The optical assembly of claim 3 , wherein the source signal includes a constant voltage source signal that is received from a host power supply.
5. The optical assembly of claim 3 , wherein the PWM output signal includes a high frequency PWM output signal configured to reduce physical sizes of components of the filter and a physical size of the switch.
6. The optical assembly of claim 2 , wherein the PWM operates at a frequency greater than about 50 megahertz (MHz).
7. The optical assembly of claim 2 , wherein the PWM is constructed using low-parasitic complementary metal-oxide-semiconductor (CMOS) technology.
8. The optical assembly of claim 1 , wherein the one or more integrated power supplies are included in
a step-down.
9. The optical assembly of claim 1 , wherein:
the one or more integrated power supplies include a first integrated power supply that is included in a step-down converter; and
the other integrated components include a microcontroller, a digital to analog converter, an analog to digital converter, electrically erasable programmable read-only memory (EEPROM), an amplifier controller, an inrush controller, and temperature sense circuitry.
10. The optical assembly of claim 1 , wherein:
the one or more integrated power supplies include a first integrated power supply that is included in a step-down converter;
the other integrated components include a modulator driver, a linear operational amplifier, a bias tee, and a microcontroller; and
the substrate includes a substrate transmission line.
11. The optical assembly of claim 1 , wherein:
the one or more integrated power supplies include a first integrated power supply that is included in a multi-output DC-DC section and a second integrated power supply that is included in a step down inverter; and
the other integrated components include a driver, a CDR, a microcontroller, a modulator bias monitor, and a bias tee.
12. The optical assembly of claim 1 , wherein the substrate comprises one of a low temperature co-fired ceramic (LTCC) substrate and a high temperature co-fired ceramic (HTCC) substrate.
13. The optical assembly of claim 1 , further comprising a printed circuit board (PCB) to which the substrate is mounted.
14. An optical subassembly comprising:
a printed circuit board (PCB);
a substrate that is mounted to the PCB; and
an integrated circuit (IC) mounted to the substrate, wherein the IC includes:
one or more integrated power supplies that each include a filter and a pulse width modulator (PWM) configured to generate a PWM output signal that controls entry of a source signal through the filter,
wherein:
the filter includes an IC passive component having a first capacity and a substrate integrated passive component having a second capacity;
the first capacity and the second capacity are configured based on a frequency of the PWM output signal and a current of the source signal; and
the filter is configured to modify the source signal to generate an output signal of the integrated power supply; and
other integrated components that are configured to receive the output signal from the filter and to operate based on the output signal, the other integrated components being integrated into the IC.
15. The optical subassembly of claim 14 , wherein:
the IC passive component is located in the IC; and
the substrate integrated passive component is located in the substrate.
16. The optical subassembly of claim 14 , wherein:
the PWM includes a plurality of transistors arranged between a voltage source and a ground and an XOR gate configured to receive a first clock signal and a second clock signal generated by cycling one or more sets of transistors of the plurality of transistors;
the one or more sets of transistors includes a first set of transistors and a second set of transistors;
the first set of transistors are configured to be cycled to generate the first clock signal;
the second set of transistors are configured to be cycled to generate the second clock signal; and
the PWM output signal includes a duty cycle which is greater than either a frequency of the first clock signal or a frequency of the second clock signal.
17. The optical subassembly of claim 16 , wherein:
the one or more integrated power supplies include a first integrated power supply that is included in a step-down converter; and the other integrated components include a microcontroller, a digital to analog converter, an analog to digital converter, electrically erasable programmable read-only memory (EEPROM), an amplifier controller, an inrush controller, and temperature sense circuitry;
the one or more integrated power supplies include a first integrated power supply that is included in a step-down converter; and the other integrated components include a modulator driver, a linear operational amplifier, a bias tee, and a microcontroller; and the substrate includes a substrate transmission line; or
the one or more integrated power supplies include a first integrated power supply that is included in a multi-output DC-DC section and a second integrated power supply that is included in a step down inverter; and the other integrated components include a driver, a CDR, a microcontroller, a modulator bias monitor, and a bias tee.
18. The optical subassembly of claim 16 , wherein:
the source signal includes a constant voltage source signal that is received from a host power supply;
the source signal is received from a host power supply and has a voltage of about 3.3 volts; and
the PWM output signal includes a frequency of above 50 megahertz.
19. The optical subassembly of claim 16 , wherein:
the IC is constructed using an orthogonal gate extended drain complementary metal-oxide-semiconductor (OG EDCMOS) technology; and
the other integrated components are constructed using complementary metal-oxide-semiconductor (CMOS), Bipolar CMOS (BiCMOS), extended drain CMOS (EDMOS), OG EDMOS, or Silicon-Germanium (SiGe) heterojunction bipolar transistor (HBT).
20. The optical subassembly of claim 16 , wherein:
the substrate includes a substrate transmission line;
the source signal enters the IC through the active switch triggered by the PWM, passes through the active switch, and enters the IC passive component;
a first intermediate signal that is representative of the source signal exits the IC passive component and is communicated across the substrate via the substrate transmission line to a PCB passive component that is integrated on the PCB; and
a second intermediate signal that is representative of the first intermediate signal exits the PCB passive component and is communicated via the substrate transmission line to at least one of the other integrated components.