Variable resistance memory device and method of manufacturing the same
View Patent ↗A variable resistance memory device and a method of manufacturing the same are provided. The variable resistance memory device may include a multi-layered insulating layer formed on a semiconductor substrate, on which a lower electrode is formed. The multi-layered insulating layer may include a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole. A variable resistance material layer may be formed in the second hole to contact the lower electrode, and an upper electrode may be formed in the first hole to contact the variable resistance material layer.
1. A method of manufacturing a semiconductor integrated circuit device, the method comprising:
forming a multi-layered structure by alternately forming a first layer and a second layer on a semiconductor substrate;
forming a first hole in the multi-layered structure by etching a portion of the multilayered structure, the first hole including a sidewall with protruding portions; and
forming a spacer in a lower portion of the first hole, thereby defining a second hole by the spacer,
wherein the protruding portions of the sidewall of the first hole are formed by selectively oxidizing the second layer and removing an oxidized portion of the second layer.
2. The method of claim 1 , wherein the second layer has an etching selectivity being different from that of the first layer.
3. The method of claim 1 , wherein the first layer includes a nitride material and the second layer includes a polysilicon material.
4. The method of claim 1 , further comprising: after the forming a first hole and before the forming the spacer,
forming an oxide layer along an inner sidewall of the first hole.
5. The method of claim 4 , wherein the oxide layer is formed by an atomic layer deposition (ALD).
6. The method of claim 1 , wherein the forming the spacer includes:
filing the first hole with a spacer material; and
etching the spacer material thereby defining the second hole;
wherein the spacer material is formed to include a void when the spacer material is formed, the void formed due to the protruding portions, and the protruding portions are removed when the spacer is etched.
7. The method of claim 1 , wherein the semiconductor substrate includes a lower electrode and the lower electrode is exposed by the first and second holes.
8. The method of claim 7 , further comprising:
filling a variable resistance material in the first and second holes, the filed in variable resistance material in direct contact with the lower electrode; and
etching the variable resistance material to form a variable resistance layer within the second hole, as a remaining portion of the variable resistance material, which variable resistance layer remains in contact with the lower electrode.
9. The method of claim 8 , further comprising:
forming an upper electrode in the first hole.