Variable resistance memory device with variable resistance material layer

1. A variable resistance memory device, comprising:

a multi-layered structure formed on a semiconductor substrate, on which a lower electrode is formed, the multi-layered structure including a first hole and a second hole, concentrically formed therein, to expose the lower electrode, wherein a diameter of the first hole is larger than a diameter of the second hole and a height of the second hole is lower than that of the first hole;

a variable resistance material layer formed in the second hole to contact the lower electrode;

an upper electrode formed in the first hole to contact the variable resistance material layer;

a spacer formed to define the second hole; and

an oxide layer formed between the multi-layered structure and the upper electrode and between the multi-layered structure and the spacer.

2. The variable resistance memory device of claim 1 , wherein the multi-layered structure includes:

a first layer formed on the semiconductor substrate, the first layer including a first material; and

a second layer formed on the first layer and including a second material having an etch selectivity that is different than an etch selectivity of the first material,

wherein the first layer and the second layer are alternately stacked to form a plurality of layers.

3. The variable resistance memory device of claim 2 , wherein the first layer includes a nitride, and the second layer includes polysilicon.

4. The variable resistance memory device of claim 1 , wherein the oxide layer is formed from a portion of the second layer that is oxidized.

5. The variable resistance memory device of claim 4 , wherein the spacer is formed of a same material as the first layer.

6. A variable resistance memory device, comprising:

a semiconductor substrate including a lower electrode;

a multi-layered structure formed on the semiconductor substrate, wherein the multi-layered structure includes a first hole, the first hole extends to the lower electrode; and

a spacer formed at an inner sidewall of the first hole, wherein a second hole is defined by the spacer and a height of the spacer is lower than that of the first hole;

a variable resistance material layer formed in the second hole to contact the lower electrode; and

an oxide layer formed between the multi-layered structure and the spacer.

7. The variable resistance memory device of claim 6 , wherein a height of the spacer is same as that of the variable resistance material layer.

8. The variable resistance memory device of claim 6 , further comprising:

an upper electrode formed in the first hole to contact the variable resistance material layer.

9. The variable resistance memory device of claim 8 , further comprising:

an oxide layer formed between the multi-layered structure and the upper electrode.