Backside illuminated global shutter pixel with active reset
View Patent ↗An image sensor may include an array of pixels arranged in rows and columns. The array of pixels may operate in a global shutter mode. Each pixel in the array of pixels may have a floating diffusion node for storing charge and may include an active reset circuit that acts as an inverting amplifier and that resets the floating diffusion node to a predetermined reference voltage, which eliminates the need for correlated double sampling readout. A sampling circuit may be coupled to the active reset circuit. The sampling circuit may sample and store signals that correspond to the amount of charge stored at the floating diffusion node. The sampling circuit may pass stored signals to a column sensing line through an amplifier. The amplifier may include a source follower transistor that provides proportional amplification to the stored signals and may include an active reset circuit for resetting the sampling circuit.
1. An image sensor pixel comprising:
a photosensitive element that generates charge in response to incident light;
a floating diffusion node coupled to the photosensitive element;
an active reset circuit coupled to the floating diffusion node that sets the floating diffusion node to a voltage level during pixel reset operations, wherein the active reset circuit comprises:
a first transistor having a gate coupled to a reference voltage;
a second transistor having a gate coupled to the floating diffusion node, a source terminal coupled to a voltage supply, and a drain terminal coupled to a ground through the first transistor; and
a reset transistor coupled between the floating diffusion node and the drain terminal of the second transistor;
a column sensing line coupled to the active reset circuit; and
a sampling circuit interposed between the column sensing line and the source terminal of the second transistor.
2. The image sensor pixel defined in claim 1 , wherein the first transistor is an NMOS transistor.
3. The image sensor pixel defined in claim 1 , wherein the second transistor is a PMOS transistor.
4. The image sensor pixel defined in claim 1 , wherein the sampling circuit comprises:
a sampling transistor;
a sampling capacitor having a first terminal coupled to the source terminal of the second transistor through the sampling transistor and having a second terminal coupled to ground; and
an amplifier interposed between the first terminal of the sampling capacitor and the column sensing line.
5. The image sensor pixel defined in claim 4 , wherein the sampling transistor is a PMOS sampling transistor.
6. The image sensor pixel defined in claim 4 , wherein the amplifier comprises:
a source follower transistor having a gate terminal coupled to the first terminal of the sampling capacitor, wherein the source follower transistor is interposed between the voltage supply and the column sensing line; and
a row select transistor interposed between the source follower transistor and the column sensing line.
7. The image sensor pixel defined in claim 6 , wherein the source follower transistor is a PMOS source follower transistor.
8. The image sensor pixel defined in claim 6 , wherein the source follower transistor is an NMOS source follower transistor.
9. An image sensor pixel comprising:
a photosensitive element that generates charge in response to incident light;
a floating diffusion node coupled to the photosensitive element;
an active reset circuit coupled to the floating diffusion node that sets the floating diffusion node to a voltage level during pixel reset operations, wherein the active reset circuit comprises:
a first transistor having a gate coupled to a reference voltage;
a second transistor having a gate coupled to the floating diffusion node, a source terminal coupled to a voltage supply, and a drain terminal coupled to a ground through the first transistor; and
a reset transistor coupled between the floating diffusion node and the drain terminal of the second transistor;
a column sensing line coupled to the active reset circuit; and
a pre-charge transistor, wherein the source terminal of the second transistor is coupled to the voltage supply through the pre-charge transistor.
10. An imaging system comprising:
an array of imaging pixels arranged in rows and columns, wherein each imaging pixel in the array of imaging pixels comprises:
a photodiode that accumulates charge in response to incident light;
a transfer transistor coupled to the photodiode;
a floating diffusion region coupled to the photodiode through the transfer transistor;
an inverting amplifier coupled to the floating diffusion region; and
a column sensing line coupled to the inverting amplifier, wherein the array of imaging pixels operates in a global shutter mode, and wherein the inverting amplifier comprises:
a p-channel gain transistor having a gate coupled to the floating diffusion region, wherein the p-channel gain transistor has a source terminal coupled to the column sensing line;
an n-channel load transistor interposed between a drain terminal of the p-channel gain transistor and ground, wherein the n-channel load transistor has a gate terminal that receives a reference voltage; and
a reset transistor coupled between the floating diffusion region and the p-channel gain transistor.
11. The imaging system defined in claim 10 , further comprising:
an anti-blooming transistor interposed between the photodiode and a voltage supply.
12. The imaging system defined in claim 10 , wherein the transfer transistor is interposed between the photodiode and the floating diffusion region.