Display device
View Patent ↗The plurality of stages of circuit blocks of a driver circuit in a display device include a first transistor and a second transistor. The first transistor is connected at its gate with a first node and controls conductivity between a scanning signal line and a first clock signal line applied with a first clock signal. The first node is at an active potential when at least any one signal of signals output from one stage in each of a forward direction and a reverse direction is at the active potential. The second transistor is connected at its gate with the first node and controls conductivity between the first clock signal line and an input signal line of another stage of circuit block.
1. A display device comprising:
a plurality of pixels including a pixel transistor respectively,
a plurality of scanning signal lines connecting to the pixel transistor of the plurality of pixels, and
a driver circuit sequentially applying an active potential to the plurality of scanning signal lines, wherein
the driver circuit includes a plurality of stages of circuit blocks as circuits respectively applying the active potential to the plurality of scanning signal lines, a clock signal line applying a clock signal to the plurality of stages, an active signal line applying the active potential, and an inactive signal line applying an inactive potential,
the clock signal includes the active potential which can turn on the pixel transistor and the inactive potential which can turn off the pixel transistor,
at least one stage of circuit block of the plurality of stages of circuit blocks includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first node, a second node, and a transfer node,
the first transistor connects the clock signal line and the scanning signal line, and applies a first clock signal of the clock signal to the scanning signal line when the first transistor is an ON state,
the second transistor connects the clock signal line and the transfer electrode which is electrically connected to the first node of a next stage of the plurality of stages, and applies the first clock signal to the first node of the next stage when the second transistor is an ON state,
the first node is connected to a gate of the first transistor of a present stage and to a gate of the second transistor of the present stage,
the third transistor connects the scanning signal line and the inactive signal line when the third transistor is an ON state,
the fourth transistor connects the inactive signal line and the first node of the next stage when the fourth transistor is an ON state,
the second node is connected to a gate of the third transistor of the present stage and a gate of the fourth transistor of the present stage, and
the transfer electrode is not directly connected to the scanning signal line.
2. The display device according to claim 1 , further comprising a fifth transistor, wherein
the fifth transistor connects the first node and the gate of the first transistor,
the fifth transistor has a gate which is connected to the active signal line, and
the fifth transistor has a double-gate structure.
3. The display device according to claim 1 , wherein
the second transistor connects the clock signal line and the first node of a previous stage of the plurality of stages, and applies the first clock signal to the first node of the previous stage when the second transistor is an ON state.
4. The display device according to claim 1 , wherein
the fourth transistor connects the inactive signal line and the first node of a previous stage when the fourth transistor is an ON state.
5. The display device according to claim 1 , wherein
the active potential of the clock signal is different voltage of the active potential of the active signal line.
6. A display device comprising:
a plurality of pixels including a pixel transistor respectively,
a plurality of scanning signal lines connecting to the pixel transistor of the plurality of pixels and arranged in a first direction, and
a driver circuit sequentially applying an active potential to the plurality of scanning signal lines in order of a forward direction along the first direction and a reverse direction along the reverse direction of the first direction, wherein
the driver circuit includes a plurality of stages of circuit blocks as circuits respectively applying the active potential to the plurality of scanning signal lines, a pulse signal line applying a pulse signal to the plurality of stages, an active signal line applying the active potential, and an inactive signal line applying an inactive potential,
the pulse signal includes the active potential which can turn on the pixel transistor and the inactive potential which can turn off the pixel transistor,
at least one stage of circuit block of the plurality of stages of circuit blocks includes a first transistor, a second transistor, a third transistor, a fourth transistor, fifth transistor, a first node, a second node, a forward input terminal, a reverse input terminal, and a transfer electrode,
the first transistor connects the pulse signal line and the scanning signal line, and applies the pulse signal to the scanning signal line when the first transistor is an ON state,
the first node is connected to a gate of the first transistor of a present stage,
the second transistor connects the forward input terminal and the first node of the present stage,
the forward input terminal of the present stage is directly connected to the transfer electrode of a previous stage,
the third transistor connects the scanning signal line and the inactive signal line when the third transistor is an ON state,
the second node connects a gate of the third transistor,
the fourth transistor connects the reverse input terminal and the first node of the present stage,
the reverse input terminal is directly connected to the transfer electrode of a next stage,
the fifth transistor connects the first node and the gate of the first transistor,
the fifth transistor has a gate which is connected to the active signal line, and
the transfer electrode is not directly connected to the scanning signal line.
7. The display device according to claim 6 , wherein
the fifth transistor has a double-gate structure.
8. The display device according to claim 6 , wherein
the second transistor has a double-gate structure.
9. The display device according to claim 6 , wherein
the fourth transistor has a double-gate structure.
10. The display device according to claim 6 , wherein
the active potential of the pulse signal is different voltage of the active potential of the active signal line.