Semiconductor device and driving method thereof

1. A semiconductor device comprising:

a sense amplification unit suitable for sensing and amplifying data loaded on a data line pair;

a pull-up driving unit suitable for supplying a first voltage to a pull-up power line of the sense amplification unit as a pull-up driving voltage during an initial period of an active mode, supplying a second voltage lower than the first voltage to the pull-up power line as the pull-up driving voltage during a remaining period of the active mode, and supplying a third voltage higher than the first voltage to the pull-up power line as the pull-up driving voltage during an initial period of a precharge;

a pull-down driving unit suitable for supplying a fourth voltage to a pull-down power line of the sense amplification unit as a pull-down driving voltage during the active mode and the initial period of the precharge mode; and

a post over-driving control unit suitable for adjusting the initial period of the precharge mode by detecting a voltage level of the pull-up power line.

2. The semiconductor device of claim 1 , wherein the pull-up driving unit comprises:

a first pull-up driving section suitable for driving the pull-up power line by the first voltage and the second voltage in response to a first pull-up driving signal in the active mode; and

a second pull-up driving section suitable for driving the pull-up power line by the third voltage in response to a second pull-up driving signal during the initial period of the precharge mode,

wherein the post over-driving control unit adjusts a pulse width of the second pull-up driving signal.

3. The semiconductor device of claim 2 , wherein the post over-driving control unit comprises:

a set pulse generating unit suitable for detecting the driven level of the pull-up power line during the initial period of the precharge mode, and generating a set pulse in response to the detected driven level; and

a third pull-up driving signal generating unit suitable for generating the third pull-up driving signal in response to the set pulse and a reset pulse.

4. The semiconductor device of claim 3 , wherein the set pulse generating unit comprises:

a reference voltage generation section suitable for dividing the third voltage to generate a first reference voltage and a second reference voltage that is higher than the first reference voltage;

a comparison section suitable for comparing a voltage level of the pull-up power line with the first and second reference voltages;

a determining section suitable for determining the voltage level of the pull-up power line based on the comparison result of the comparison section to generate detection signals; and

a pulse width control section suitable for adjusting an activation timing of the set pulse in response to the detection signals.

5. The semiconductor device of claim 4 , wherein the pulse width control section comprises:

an up/down counter suitable for performing a counting up/down operation in response to the detection signals to generate counting signals;

a latch suitable for latching the counting signals to output a pulse width information;

a decoder suitable for decoding the outputted pulse width information to generate pulse signals; and

an output part suitable for outputting the set pulse having an activation timing corresponding to an activated signal of the pulse signals.

6. The semiconductor device of claim 4 , wherein the comparison section comprises:

a first comparator suitable for comparing the voltage level of the pull-up power line with the first reference voltage; and

a second comparator suitable for comparing the voltage level of the pull-up power line with the second reference voltage.

7. The semiconductor device of claim 5 , wherein the determining section activates a first detection signal when the voltage level of the pull-up power line is determined to be lower than the first reference voltage, activates a second detection signal when the voltage level of the pull-up power line is determined to be higher than the second reference voltage, and activates a third detection signal when the voltage level of the pull-up power line is determined to be higher than the first reference voltage and lower than the second reference voltage.

8. The semiconductor device of claim 7 , wherein the up/down counter performs the counting up/down operation in response to the first and second detection signals and holds the counting up/down operation when the third detection signal is activated.

9. The semiconductor device of claim 1 , further comprising:

a first precharge unit suitable for precharging the data line pair by a precharge voltage during a remaining period of the precharge mode; and

a second precharge unit suitable for precharging the pull-up power line and the pull-down power line by the precharge voltage during the remaining period of the precharge mode,

wherein the precharge voltage has a voltage level corresponding to a half of the first voltage.

10. The semiconductor device of claim 9 , wherein the first voltage includes a core voltage generated by voltage-dropping a power supply voltage VDD supplied from an external, the second voltage includes a boosted voltage generated by boosting the power supply voltage, the third voltage includes a ground voltage supplied from the external, and the precharge voltage includes a bit line precharge voltage.

11. A semiconductor device comprising:

a bit line pair;

a memory cell coupled to one of the bit line pair;

a sense amplification unit suitable for sensing and amplifying data loaded on the bit line pair;

a pull-up driving unit suitable for supplying a first voltage to a pull-up power line of the sense amplification unit as a pull-up driving voltage during an initial period of an active mode, supplying a second voltage lower than the first voltage to the pull-up power line as the pull-up driving voltage during a remaining period of the active mode, and supplying a third voltage higher than the first voltage to the pull-up power line as the pull-up driving voltage during an initial period of a precharge mode;

a pull-down driving unit suitable for supplying a fourth voltage to a pull-down power line of the sense amplification unit as a pull-down driving voltage during the active mode and the initial period of the precharge mode;

a post over-driving control unit suitable for adjusting the initial period of the precharge mode by detecting a voltage level of the pull-up power line; and

a first precharge unit suitable for precharging the bit line pair by a precharge voltage during a remaining period of the precharge mode,

wherein the third voltage is higher than the first voltage and the second voltage (VCORE).

12. The semiconductor device of claim 11 , wherein the pull-up driving unit comprises:

a first pull-up driving section suitable for driving the pull-up power line by the first voltage in response to a first pull-up driving signal during the initial period of the active mode;

a second pull-up driving section suitable for driving the pull-up power line by the second voltage in response to a second pull-up driving signal during the remaining period of the active mode; and

a third pull-up driving section suitable for driving the pull-up power line by the third voltage in response to a third pull-up driving signal during the initial period of the precharge mode.

13. The semiconductor device of claim 12 , wherein the post over-driving control unit comprises:

a set pulse generating unit suitable for detecting the driven level of the pull-up power line during the initial period of the precharge mode, and generating a set pulse in response to the detected driven level; and

a third pull-up driving signal generating unit suitable for generating the third pull-up driving signal in response to the set pulse and a reset pulse.

14. The semiconductor device of claim 13 , wherein the post over-driving control unit comprises:

a reference voltage generation section suitable for dividing the third voltage to generate a first reference voltage and a second reference voltage that is higher than the first reference voltage;

a comparison section suitable for comparing a voltage level of the pull-up power line with the first and second reference voltages;

a determining section suitable for determining the voltage level of the pull-up power line based on the comparison result of the comparison section to generate detection signals; and

a pulse width control section suitable for adjusting an activation timing of the set pulse in response to the detection signals.

15. The semiconductor device of claim 13 , wherein the pulse width control section comprises:

an up/down counter suitable for performing a counting up/down operation in response to the detection signals to generate counting signals;

a latch suitable for latching the counting signals to output a pulse width information;

a decoder suitable for decoding the outputted pulse width information to generate pulse signals; and

an output part suitable for outputting the set pulse having an activation timing corresponding to an activated signal of the pulse signals.

16. The semiconductor device of claim 13 , wherein the comparison section comprises:

a first comparator suitable for comparing the voltage level of the pull-up power line with the first reference voltage; and

a second comparator suitable for comparing the voltage level of the pull-up power line with the second reference voltage.

17. The semiconductor device of claim 15 , wherein the determining section activates a first detection signal when the voltage level of the pull-up power line is determined to be lower than the first reference voltage, activates a second detection signal when the voltage level of the pull-up power line is determined to be higher than the second reference voltage, and activates a third detection signal when the voltage level of the pull-up power line is determined to be higher than the first reference voltage and lower than the second reference voltage.

18. The semiconductor device of claim 17 , wherein the up/down counter performs the counting up/down operation in response to the first and second detection signals and holds the counting up/down operation when the third detection signal is activated.

19. The semiconductor device of claim 13 , wherein the first voltage includes a power supply voltage supplied from an external and the fourth voltage includes a ground voltage supplied from the external.

20. The semiconductor device of claim 19 , wherein the second voltage includes a core voltage generated by voltage-dropping the power supply voltage and the third voltage includes a boosted voltage generated by boosting the power supply voltage,

wherein the precharge voltage has a voltage level corresponding to a half of the core voltage.

21. The semiconductor device of claim 11 , further comprising:

a second precharge unit suitable for precharging the pull-up power line and the pull-down power line by the precharge voltage during the remaining period of the precharge mode.