Bandwidth amplification using pre-clocking
Technologies are generally described herein for bandwidth amplification using a pre-clock signal to latch data at a latch in an input register of a sender section while passing the data through a multiplexer of the sender section in a serial manner. In some configurations, pre-clocking the multiplexer can allow for parallel operations to occur within the sender section, thus hiding or reducing the effects of certain serialization delays associated with the multiplexer. Furthermore, the pre-clocking of the multiplexer, in some configurations, hides or reduces the register latch hold and setup delays. A method may create three levels of parallelization of latencies between a sender circuit, a serialization circuit, and a receiver circuit by overlapping them at same time.
1. A method to increase a rate or an amount of a data transfer, the method comprising:
receiving, at an input register of a sender section, a pre-clock signal that has a first frequency;
receiving, at the input register, at least one input data;
latching the at least one input data in the input register using the pre-clock signal as an activation signal to provide latched data; and
selecting, at a multiplexer of the sender section, the latched data to be output to a receiver section as serialized data output at approximately a same time the latched data is latched and becomes available in the input register using bus signals synchronized with the pre-clock signal to generate the serialized data output,
wherein the bus signals comprise a first bus signal and a second bus signal that are approximately one half of the first frequency.
2. The method of claim 1 , further comprising:
generating the bus signals from the pre-clock signal.
3. The method of claim 1 , wherein:
the first bus signal is approximately ninety degrees out of phase relative to the second bus signal using a pre-clock multiplier of two,
the first bus signal is approximately sixty degrees out of phase relative to the second bus signal using a pre-clock multiplier of three, or
the first bus signal is approximately forty-five degrees out of phase relative to the second bus signal using a pre-clock multiplier of four.
4. The method of claim 1 , further comprising:
receiving the serialized data output at the receiver section.
5. The method of claim 4 , further comprising:
latching the received serialized data output in a receiver latch selected from receiver latches, using the bus signals.
6. The method of claim 5 , wherein using the bus signals to latch the serialized data in the selected receiver latch comprises latching the serialized data at:
a first output latch of the receiver latches configured to latch data on a rising edge of the first bus signal of the bus signals;
a second output latch of the receiver latches configured to latch data on a falling edge of the first bus signal of the bus signals;
a third output latch of the receiver latches configured to latch data on a rising edge of the second bus signal of the bus signals; and
a fourth output latch of the receiver latches configured to latch data on a falling edge of the second bus signal of the bus signals.
7. A circuit apparatus, comprising:
a sender section configured to receive data from a memory, wherein the sender section comprises:
an input register configured to:
selectively receive inputs from the memory, wherein the inputs include the data and a pre-clock signal; and
provide a data output; and
a data multiplexer coupled to the input register and configured to:
receive other inputs that include the data output, the pre-clock signal, and bus signals, wherein the pre-clock signal and the bus signals are configured to synchronize the input register and the data multiplexer, and wherein the data multiplexer is configured to select data from a latch in the input register at approximately a same time the data is latched at the latch in the input register; and
provide a serialized data output; and
a receiver section coupled to the sender section and configured to:
receive the serialized data output from the sender section, wherein the receiver section is operative to be synchronized with the data multiplexer and comprises latches, and wherein the receiver section is configured to receive the pre-clock signal, the bus signals, and the serialized data output.
8. The circuit apparatus of claim 7 , wherein:
the data is requested from the memory by a core of a multi-core processor, and
the receiver section is configured to provide the serialized data output to the core.
9. The circuit apparatus of claim 7 , wherein the input register comprises pre-clock synchronization circuits configured to selectively receive data from a data bus.
10. The circuit apparatus of claim 9 , wherein at least some of the pre-clock synchronization circuits comprise:
a synchronization multiplexer configured to:
receive as an input one of the bus signals and the data from the data bus; and
provide another data output; and
a latch that includes a synchronization latch configured to:
receive the another data output from the synchronization multiplexer and the pre-clock signal; and
provide an additional data output to the data multiplexer.
11. The circuit apparatus of claim 7 , wherein the sender section further comprises:
a pre-clock register coupled to the input register and the data multiplexer, wherein the pre-clock register is configured to generate the bus signals from the pre-clock signal.
12. The circuit apparatus of claim 11 , wherein the pre-clock register comprises pre-clock flip-flops, and wherein the pre-clock flip-flops are configured to:
receive as an input the pre-clock signal; and
output the bus signals.
13. The circuit apparatus of claim 12 , wherein:
at least one of the pre-clock flip-flops comprises a trailing edge triggered flip-flop and at least another one of the pre-clock flip-flops comprises a leading edge triggered flip-flop, and
a combination of the trailing edge triggered flip-flop and the leading edge triggered flip-flop is configured to cause at least two of the bus signals to be approximately ninety degrees out of phase with each other.
14. The circuit apparatus of claim 7 , wherein the latches of the receiver section comprise:
a first output latch of receiver latches configured to latch data on a rising edge of a first signal of the bus signals;
a second output latch of the receiver latches configured to latch data on a falling edge of the first signal of the bus signals;
a third output latch of the receiver latches configured to latch data on a rising edge of a second signal of the bus signals; and
a fourth output latch of the receiver latches configured to latch data on a falling edge of the second signal of the bus signals.
15. A system, comprising:
a bus;
a central processing unit coupled to the bus; and
a memory controller coupled to the bus, wherein the memory controller is configured to control a circuit, and wherein the circuit comprises:
a sender section configured to receive data from a memory in response to a request for the data from a requester component, wherein the sender section includes:
an input register configured to:
selectively receive data from the memory;
receive a pre-clock signal input; and
provide a data output;
a data multiplexer coupled to the input register and configured to:
receive the data output, the pre-clock signal, and bus signals from the input register, wherein the pre-clock signal and the bus signals are configured to synchronize the input register and the data multiplexer, and wherein the data multiplexer is configured to select data in the input register at approximately a same time the data is latched in the input register; and
provide a serialized data output; and
a receiver section that is coupled to the sender section and is synchronized with the data multiplexer,
wherein the receiver section is configured to:
receive the serialized data output from the sender section to be sent to the requester component;
receive the pre-clock signal from the data multiplexer; and
output data,
wherein the receiver section includes latches, and
wherein the latches include:
a first output latch configured to latch data on a rising edge of a first signal of the bus signals;
a second output latch of the receiver latches configured to latch data on a rising edge of a second signal of the bus signals;
a third output latch of the receiver latches configured to latch data on a falling edge of the second signal of the bus signals; and
a fourth output latch of the receiver latches configured to latch data on a falling edge of the first signal of the bus signals.
16. The system of claim 15 , wherein the requester component includes a core of the central processing unit.
17. The system of claim 15 , wherein the input register comprises pre-clock synchronization circuits configured to selectively receive data from the bus.
18. The system of claim 17 , wherein at least some of the pre-clock synchronization circuits comprise:
a synchronization multiplexer configured to:
receive one of the bus signals and the data from the bus; and
provide another output of data; and
a synchronization latch coupled to the synchronization multiplexer and configured to:
receive the another output of data from the synchronization multiplexer and the pre-clock signal; and
provide an additional output to the data multiplexer.
19. The system of claim 15 , wherein at least two of the bus signals are approximately ninety degrees out of phase from each other.