Array substrates and the manufacturing method thereof

1. A manufacturing method of array substrates, comprising:

depositing a conductive layer on a substrate, and forming three poles of at least one thin film transistor (TFT), a first signal line, and a second signal line by etching the conductive layer via a first mask, wherein the first signal line comprises a first portion and a second portion respectively at two sides of the second signal line;

depositing an intermediate layer in sequence, and forming a first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask; and

depositing a conductive electrode, and forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask.

2. The manufacturing method as claimed in claim 1 , wherein the first portion of the first signal line electrically connects to a first pole of the TFT, the second signal line electrically connects to a second pole of the TFT, and the intermediate layer comprises an insulation layer, an active layer, an ohmic contact layer, and a passivation layer stacked in sequence;

the step of forming a first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask further comprises forming a second connecting bridge connecting the second pole and a third pole of the TFT by etching the intermediate layer via the second mask;

the step of forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask further comprises disconnecting the conductive electrode, the passivation layer, and the second pole and the third pole corresponding to the ohmic contact layer by etching the second connecting bridge via the third mask.

3. The manufacturing method as claimed in claim 2 , wherein the step of forming the second connecting bridge connecting the second pole and the third pole of the TFT by etching the intermediate layer via the second mask further comprises:

adopting HF to etch edges of the passivation layer and the insulation layer of the second connecting bridge such that the active layer and the ohmic contact layer of the second connecting bridge protrude outward to form at least one contact ring.

4. The manufacturing method as claimed in claim 3 , wherein the conductive electrode on the second connecting bridge is arranged on the contact ring such that the conductive electrode electrically connects to the contact ring, the second pole, and the third pole.

5. The manufacturing method as claimed in claim 4 , wherein the first pole, the second pole, and the third pole of the TFT are respectively a gate, a source, and a drain, and the first signal line is a data line, and the second signal line is a signal line.

6. The manufacturing method as claimed in claim 1 , wherein the step of forming the first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask further comprises forming a capacitance isolation structure on the first portion by etching the intermediate layer via the second mask;

the step of forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via the third mask further comprises forming a storage capacitance electrode on the capacitance isolation structure by etching the conductive electrode via the third mask.

7. The manufacturing method as claimed in claim 1 , wherein the first pole, the second pole, and the third pole of the TFT are respectively a gate, a source, and a drain, and the first signal line is a signal line, and the second signal line is a data line.

8. An array substrate manufactured by a manufacturing method, and the method comprising:

depositing a conductive layer on a substrate, and forming three poles of at least one thin film transistor (TFT), a first signal line, and a second signal line by etching the conductive layer via a first mask, wherein the first signal line comprises a first portion and a second portion respectively at two sides of the second signal line;

depositing an intermediate layer in sequence, and forming a first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask; and

depositing a conductive electrode, and forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask.

9. The array substrate as claimed in claim 8 , wherein the first portion of the first signal line electrically connects to a first pole of the TFT, the second signal line electrically connects to a second pole of the TFT, and the intermediate layer comprises an insulation layer, an active layer, an ohmic contact layer, and a passivation layer stacked in sequence;

the step of forming a first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask further comprises forming a second connecting bridge connecting the second pole and a third pole of the TFT by etching the intermediate layer via the second mask;

the step of forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask further comprises disconnecting the conductive electrode, the passivation layer, and the second pole and the third pole corresponding to the ohmic contact layer by etching the second connecting bridge via the third mask.

10. The array substrate as claimed in claim 9 , wherein the step of forming the second connecting bridge connecting the second pole and the third pole of the TFT by etching the intermediate layer via the second mask further comprises:

adopting HF to etch edges of the passivation layer and the insulation layer of the second connecting bridge such that the active layer and the ohmic contact layer of the second connecting bridge protrude outward to form at least one contact ring.

11. The array substrate as claimed in claim 10 , wherein the conductive electrode on the second connecting bridge is arranged on the contact ring such that the conductive electrode electrically connects to the contact ring, the second pole, and the third pole.

12. The array substrate as claimed in claim 8 , wherein the step of forming the first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask further comprises forming a capacitance isolation structure on the first portion by etching the intermediate layer via the second mask;

the step of forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via the third mask further comprises forming a storage capacitance electrode on the capacitance isolation structure by etching the conductive electrode via the third mask.

13. The array substrate as claimed in claim 8 , wherein the first pole, the second pole, and the third pole of the TFT are respectively a gate, a source, and a drain, and the first signal line is a signal line, and the second signal line is a data line.