IP Library Granted Patent US 9,904,352
Granted Patent B2
US 9,904,352 · App. 15/113,884 · Granted Feb 27, 2018

Processor control apparatus and processor control method

Inventor: Youhei Hara (Saitama, JP)
Assignee: CALSONIC KANSEI CORPORATION
G06F1/3296G06F1/14G06F1/3206G06F1/3228G06F11/0721G06F11/0757
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Quick Facts
Patent No.
US 9,904,352
App. No.
15/113,884
Granted
Feb 27, 2018
Kind
B2
Abstract

A control apparatus and control method for a processor can reset the processor when the processor returns from low current consumption operation mode to regular operation mode. The control apparatus ( 11 ) for a processor ( 10 ) includes a watchdog timer ( 20 ) that resets the processor ( 10 ) when a P-RUN signal from the processor ( 10 ) cannot be acquired for a predetermined time, a current monitor ( 19 ) that suspends operation of the watchdog timer ( 20 ) when output current of a power supply ( 18 ) that supplies power to the processor ( 10 ) falls below a predetermined value and starts operation of the watchdog timer ( 20 ) when the output current becomes equal to or greater than the predetermined value, and a current amplifier ( 21 ) that increases the output current to be equal to or greater than the predetermined value upon acquiring a signal for causing the processor ( 10 ) to start operating in the regular operation mode.

Claims (10)

1. A processor control apparatus for controlling a processor capable of operating while switching between a regular operation mode and a low current consumption operation mode with a lower current consumption than the regular operation mode, the processor control apparatus comprising:

a watchdog timer configured to reset the processor when a P-RUN signal from the processor cannot be acquired for a predetermined time;

a current monitor configured to suspend operation of the watchdog timer when output current of a power supply that supplies power to the processor falls below a predetermined value and to start operation of the watchdog timer when the output current becomes equal to or greater than the predetermined value; and

a current amplifier configured to increase the output current to be equal to or greater than the predetermined value upon acquiring a signal for causing the processor to start operating in the regular operation mode.

2. The processor control apparatus of claim 1 , further comprising:

a P-RUN signal detector configured to reduce or remove an increase by the current amplifier in the output current upon detecting input of the P-RUN signal.

3. A processor control method used in a control apparatus that includes a watchdog timer configured to reset a processor when a P-RUN signal from the processor cannot be acquired for a predetermined time, the processor being capable of operating while switching between a regular operation mode and a low current consumption operation mode with a lower current consumption than the regular operation mode, the processor control method comprising:

suspending operation of the watchdog timer when output current of a power supply that supplies power to the processor falls below a predetermined value;

increasing the output current to be equal to or greater than the predetermined value upon acquiring a signal for causing the processor to start operating in the regular operation mode; and

starting operation of the watchdog timer when the output current becomes equal to or greater than the predetermined value.

Assignments (2)
CHANGE OF NAME Recorded Jun 12, 2025
From: CALSONIC KANSEI CORPORATION
To: MARELLI CORPORATION
Reel/Frame 071577/0598 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2017
From: HARA, YOUHEI
To: CALSONIC KANSEI CORPORATION
Reel/Frame 043859/0670 →
Priority Claims (1)
JP 2014-012318 · Jan 27, 2014 · national
Continuity (1)
Related Publication 20160349833A1 · Dec 1, 2016