Method for producing an optoelectronic semiconductor component and optoelectronic semiconductor component

1. A method for producing an optoelectronic semiconductor component having a multiplicity of image points, the method comprising:

providing a semiconductor layer sequence having a main extension plane, wherein the semiconductor layer sequence comprises an n-conductive semiconductor layer having a base surface, an active zone disposed on a cover surface of the n-conductive semiconductor layer facing away from the base surface, and a p-conductive semiconductor layer arranged on a side of the active zone facing away from the n-conductive semiconductor layer;

applying a first layer sequence comprising a p-contacting layer and a first insulation layer, wherein the first layer sequence is divided into a plurality of regions which are arranged laterally spaced apart from one another on a cover surface of the p-conductive semiconductor layer facing away from the n-conductive semiconductor layer;

applying a second insulation layer extending substantially transversely to the main extension plane and covering all the side faces of the first layer sequence at least in places;

partially removing the p-conductive semiconductor layer and the active zone such that the n-conductive semiconductor layer is exposed in places and the p-conductive semiconductor layer and the active zone are divided into individual regions which are laterally spaced apart from one another, wherein each of the regions includes a part of the p-conductive semiconductor layer and part of the active zone;

applying an n-contacting layer and a metallization layer such that the n-contacting layer and the metallization layer each extend along the main extension plane of the semiconductor layer sequence; and

partially removing the metallization layer and the first insulation layer such that the p-contacting layer is exposed at least in places.

2. The method according to claim 1 , wherein partially removing the p-conductive semiconductor layer and the active zone comprises using the first insulation layer and the second insulation layer as a mask.

3. The method according to claim 2 , wherein partially removing the p-conductive semiconductor layer and the active zone comprises applying an etching method.

4. The method according to claim 1 , wherein partially removing the p-conductive semiconductor layer and the active zone comprises partially removing the n-conductive semiconductor layer in places forming thinned regions of the n-conductive semiconductor layer, and wherein a distance between the cover surface and the base surface of the n-conductive semiconductor layer in the thinned regions is smaller than in other, unthinned regions of the n-conductive semiconductor layer.

5. The method according to claim 1 , wherein applying the first layer sequence comprises:

applying the p-contacting layer over the whole surface onto the cover surface of the p-conductive semiconductor layer;

applying the first insulation layer over the whole surface onto a side of the p-contacting layer facing away from the n-conductive semiconductor layer;

partially removing the first insulation layer; and

partially removing the p-contacting layer, wherein the first insulation layer is used as a mask.

6. The method according to claim 1 , further comprising applying a third insulation layer extending substantially transversely to the main extension plane after partially removing the p-conductive semiconductor layer and the active zone and before applying the n-contacting layer and the metallization layer, and wherein the third insulation layer is in direct contact with the second insulation layer and the p-conductive semiconductor layer.

7. The method according to claim 1 , wherein applying the second insulation layer and/or a third insulation layer comprises:

applying the second insulation layer and/or the third insulation layer over the whole surface onto an exposed outer surface facing away from the base surface of the n-conductive semiconductor layer; and

partially removing the second insulation layer and/or the third insulation layer so that the second insulation layer and/or the third insulation layer extend substantially transversely to the main extension plane of the semiconductor layer sequence.

8. The method according to claim 7 , wherein partially removing comprises a targeted dry etching method.

9. The method according to claim 1 , further comprising immersing the optoelectronic semiconductor component in an acid bath for a predetermined time period after applying the n-contacting layer and the metallization layer, and before partially removing the metallization layer, wherein immersing removes traces of a material of the n-contacting layer and/or of the metallization layer located on the side faces of the image points.

10. The method according to claim 1 , wherein a fourth insulation layer is applied over the whole surface onto an exposed outer surface facing away from the base surface of the n-conductive semiconductor layer after applying the n-contacting layer and the metallization layer, and before partially removing the metallization layer.

11. An optoelectronic semiconductor component comprising:

a semiconductor layer sequence having a main extension plane, the semiconductor layer sequence comprising:

an n-conductive semiconductor layer formed in one piece;

an active zone and a p-conductive semiconductor layer divided into a plurality of regions which are laterally spaced apart from one another, wherein each region forms, together with the n-conductive semiconductor layer, precisely one image point;

an n-contacting layer configured to be electrically conductive, wherein a base surface of the n-contacting layer adjoins a cover surface of the n-conductive semiconductor layer;

a p-contacting layer configured to be electrically conductive, wherein a base surface of the p-contacting layer adjoins a cover surface of the p-conductive semiconductor layer; and

a third insulation layer configured to be electrically insulating and extending substantially transversely to the main extension plane of the semiconductor layer sequence,

wherein the third insulation layer is arranged between the p-conductive semiconductor layer and the n-contacting layer and directly adjoins all the lateral surfaces of the n-contacting layer and all the lateral surfaces of the p-conductive semiconductor layer,

wherein the n-contacting layer is continuous and surrounds the image points in a frame-like manner, and

wherein the cover surface of the n-conductive semiconductor layer is, in regions of the image points, at a larger distance to a base surface of the n-conductive semiconductor layer than in the region of the n-contacting layer.

12. The optoelectronic semiconductor component according to claim 11 , wherein the image points are surrounded by the third insulation layer at all the lateral side faces.

13. The optoelectronic semiconductor component according to claim 11 , further comprising a second insulation layer extending substantially transversely to the main extension plane of the semiconductor layer sequence and being arranged between the third insulation layer and the p-contacting layer.

14. The optoelectronic semiconductor component according to claim 11 , further comprising a metallization layer arranged in a perpendicular direction to the main extension plane spaced apart from the n-contacting layer and from the p-contacting layer on cover surfaces of the second and third insulation layers facing away from the n-conductive semiconductor layer, wherein the metallization layer is reflective.

15. The optoelectronic semiconductor component according to claim 11 , further comprising a fourth insulation layer completely surrounding the image points at side faces and directly adjoining the n-contacting layer, the metallization layer and the third insulation layer.

16. The optoelectronic semiconductor component according to claim 11 , wherein a first insulation layer is arranged on a cover surface of the p-contacting layer directly adjoining a second insulation layer and wherein the first insulation layer covers a maximum of 10% of the cover surface of the p-contacting layer.

17. The optoelectronic semiconductor component according to claim 11 , wherein a second insulation layer and the third insulation layer have traces of a material removal at their corners and edges facing away from the n-conductive semiconductor layer and the p-contacting layer.

18. The optoelectronic semiconductor component according to claim 11 , wherein the image points have the same geometric dimensions within a scope of production tolerances.

19. The optoelectronic semiconductor component according to claim 11 , wherein a geometric dimension of the n-contacting layer along an imaginary connection line between center points of two adjacent image points is at the most 5 μm.

20. The optoelectronic semiconductor component according to claim 11 , wherein a lateral distance between two adjacent image points along an imaginary connection line between center points of the two adjacent image points is at the most 12 μm.