IP Library Granted Patent US 9,620,499
Granted Patent B2
US 9,620,499 · App. 15/119,420 · Granted Apr 11, 2017

Semiconductor device and method of manufacturing the semiconductor device

Inventors: Yasuhiro Hirabayashi (Toyota, JP); Satoru Machida (Nagakute, JP); Yusuke Yamashita (Nagakute, JP)
Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
H01L27/0664H01L21/26513H01L29/04H01L29/1095H01L29/32H01L29/36H01L29/66348H01L29/7397H01L29/868H01L2924/13055
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Quick Facts
Patent No.
US 9,620,499
App. No.
15/119,420
Granted
Apr 11, 2017
Kind
B2
Abstract

A semiconductor device for restraining snapback is provided. The semiconductor device includes IGBT and diode regions. In a view of n-type impurity concentration distribution along a direction from a front surface to a rear surface, a local minimum value of an n-type impurity concentration is located at a border between cathode and buffer regions. A local maximum value of n-type impurity concentration is located in the buffer region. At least one of the buffer and cathode regions includes a crystal defect region having crystal defects in a higher concentration than a region therearound. A peak of a crystal defect concentration in a view of crystal defect concentration distribution along the direction from the front surface to the rear surface is located in a region on the rear surface side with respect to a specific position having the n-type impurity concentration which is a half of the local maximum value.

Claims (25)

1. A semiconductor device comprising:

a semiconductor substrate comprising an IGBT region and a diode region,

an emitter electrode provided on a front surface of the semiconductor substrate in the IGBT region;

an anode electrode provided on the front surface of the semiconductor substrate in the diode region; and

a rear electrode provided on a rear surface of the semiconductor substrate,

wherein

the IGBT region comprises:

an emitter region of an n-type and in contact with the emitter electrode;

a body region of a p-type and in contact with the emitter electrode;

an IGBT drift region of the n-type and separated from the emitter region by the body region;

a collector region of the p-type, separated from the body region by the IGBT drift region, and in contact with the rear electrode;

a gate insulating film in contact with the body region; and

a gate electrode facing the body region via the gate insulating film,

the diode region comprises:

an anode region of the p-type and in contact with the anode electrode;

a diode drift region of the n-type, bordering the anode region on a rear surface side, and connected to the IGBT drift region;

a buffer region of the n-type and bordering the diode drift region on the rear surface side; and

a cathode region of the n-type, bordering the buffer region on the rear surface side, and in contact with the rear electrode,

in a view of n-type impurity concentration distribution along a direction from the front surface to the rear surface, a local minimum value of an n-type impurity concentration is located at a border between the cathode region and the buffer region, and a local maximum value of the n-type impurity concentration is located in the buffer region,

a peak value of the n-type impurity concentration in the cathode region and the local maximum value are higher than the n-type impurity concentration in the diode drift region,

at least one of the buffer region and the cathode region comprises a crystal defect region in which crystal defects are distributed in a higher concentration than a region around the crystal defect region, and

a peak value of a crystal defect concentration in the view of crystal defect concentration distribution along the direction from the front surface to the rear surface is located in a region on the rear surface side with respect to a specific position having the n-type impurity concentration which is a half of the local maximum value, the specific position being located on a front surface side with respect to a position of the local maximum value.

2. The semiconductor device of claim 1 , wherein the peak value of the crystal defect concentration is located in the buffer region.

3. The semiconductor device of claim 2 , wherein the peak value of the crystal defect concentration is located in a region having the n-type impurity concentration which is higher than a half of the local maximum value.

4. A method of manufacturing the semiconductor device of claim 1 , the method comprising a step of implanting charged particles into the semiconductor substrate so as to form the crystal defect region.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 053727/0319 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2016
From: HIRABAYASHI, YASUHIRO; MACHIDA, SATORU; YAMASHITA, YUSUKE
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 039707/0858 →
Priority Claims (1)
JP 2014-092438 · Apr 28, 2014 · national
Continuity (1)
Related Publication 20170069625A1 · Mar 9, 2017