IP Library Granted Patent US 9,853,024
Granted Patent B2
US 9,853,024 · App. 15/124,219 · Granted Dec 26, 2017

Semiconductor device

Inventors: Masaru Senoo (Okazaki, JP); Yasuhiro Hirabayashi (Toyota, JP)
Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
H01L27/0664H01L29/0696H01L29/1095H01L29/407H01L29/7397H01L29/872
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Quick Facts
Patent No.
US 9,853,024
App. No.
15/124,219
Granted
Dec 26, 2017
Kind
B2
Abstract

A semiconductor device having a low on-voltage of IGBT and a small reverse recovery current of the diode is provided. The semiconductor device includes a semiconductor substrate having a gate trench and a dummy trench. The semiconductor substrate includes emitter, body, barrier and pillar regions between the gate trench and the dummy trench. The emitter region is an n-type region being in contact with the gate insulating film and exposed on a front surface. The body region is a p-type region being in contact with the gate insulating film at a rear surface side of the emitter region. The barrier region is an n-type region being in contact with the gate insulating film at a rear surface side of the body region and in contact with the dummy insulating film. The pillar region is an n-type region connected to the front surface electrode and the barrier region.

Claims (54)

1. A semiconductor device comprising:

a semiconductor substrate including a gate trench and a dummy trench which are provided in a front surface of the semiconductor substrate;

a front surface electrode located on the front surface of the semiconductor substrate; and

a rear surface electrode located on a rear surface of the semiconductor substrate,

wherein

a gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film are located in the gate trench,

a dummy insulating film and a dummy electrode insulated from the semiconductor substrate by the dummy insulating film and electrically separated from the gate electrode are located in the dummy trench,

the semiconductor substrate comprises:

an emitter region of n-type located between the gate trench and the dummy trench, being in contact with the gate insulating film, and exposed on the front surface of the semiconductor substrate;

a body region of p-type located between the gate trench and the dummy trench and being in contact with the gate insulating film on a rear surface side of the emitter region;

a barrier region of n-type located between the gate trench and the dummy trench and being in contact with the gate insulating film and the dummy insulating film at a rear surface side of the body region;

a pillar region of n-type located between the gate trench and the dummy trench, connected to the front surface electrode, and connected to the barrier region;

a drift region of n-type located on a rear surface side with respect to the barrier region, separated from the body region by the barrier region, and having a density of n-type impurities lower than a density of n-type impurities in the barrier region;

a collector region of p-type exposed on the rear surface of the semiconductor substrate; and

a cathode region of n-type exposed on the rear surface of the semiconductor substrate and having a density of n-type impurities higher than the density of n-type impurities in the drift region, and

the pillar region is in contact with the dummy insulating film.

2. The semiconductor device of claim 1 , wherein the semiconductor substrate includes a plurality of gate trenches and a plurality of dummy trenches which are arranged alternately and repeatedly in a cross-section orthogonal to the front surface of the semiconductor substrate.

3. A semiconductor device comprising:

a semiconductor substrate including a gate trench and a dummy trench which are provided in a front surface of the semiconductor substrate;

a front surface electrode located on the front surface of the semiconductor substrate; and

a rear surface electrode located on a rear surface of the semiconductor substrate,

wherein

a gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film are located in the gate trench,

a dummy insulating film and a dummy electrode insulated from the semiconductor substrate by the dummy insulating film and electrically separated from the gate electrode are located in the dummy trench,

the semiconductor substrate comprises:

an emitter region of n-type located between the gate trench and the dummy trench, being in contact with the gate insulating film, and exposed on the front surface of the semiconductor substrate;

a body region of p-type located between the gate trench and the dummy trench and being in contact with the gate insulating film on a rear surface side of the emitter region;

a barrier region of n-type located between the gate trench and the dummy trench and being in contact with the gate insulating film and the dummy insulating film at a rear surface side of the body region;

a pillar region of n-type located between the gate trench and the dummy trench, connected to the front surface electrode, and connected to the barrier region;

a drift region of n-type located on a rear surface side with respect to the barrier region, separated from the body region by the barrier region, and having a density of n-type impurities lower than a density of n-type impurities in the barrier region;

a collector region of p-type exposed on the rear surface of the semiconductor substrate; and

a cathode region of n-type exposed on the rear surface of the semiconductor substrate and having a density of n-type impurities higher than the density of n-type impurities in the drift region,

the semiconductor substrate further comprises an intermediate region of p-type located between the gate trench and the dummy trench and between the barrier region and the drift region and being in contact with the gate insulating film and the dummy insulating film, and

an average value of a density of p-type impurities in a portion of the intermediate region closer to the dummy trench than a center position between the gate trench and the dummy trench is higher than an average value of a density of p-type impurities in a portion of the intermediate region closer to the gate trench than the center position.

4. The semiconductor device of claim 3 , wherein the semiconductor substrate includes a plurality of gate trenches and a plurality of dummy trenches which are arranged alternately and repeatedly in a cross-section orthogonal to the front surface of the semiconductor substrate.

5. A semiconductor device comprising:

a semiconductor substrate including a gate trench and a dummy trench which are provided in a front surface of the semiconductor substrate;

a front surface electrode located on the front surface of the semiconductor substrate; and

a rear surface electrode located on a rear surface of the semiconductor substrate,

wherein

a gate insulating film and a gate electrode insulated from the semiconductor substrate by the gate insulating film are located in the gate trench,

a dummy insulating film and a dummy electrode insulated from the semiconductor substrate by the dummy insulating film and electrically separated from the gate electrode are located in the dummy trench,

the semiconductor substrate comprises:

an emitter region of n-type located between the gate trench and the dummy trench, being in contact with the gate insulating film, and exposed on the front surface of the semiconductor substrate;

a body region of p-type located between the gate trench and the dummy trench and being in contact with the gate insulating film on a rear surface side of the emitter region;

a barrier region of n-type located between the gate trench and the dummy trench and being in contact with the gate insulating film and the dummy insulating film at a rear surface side of the body region;

a pillar region of n-type located between the gate trench and the dummy trench, connected to the front surface electrode, and connected to the barrier region;

a drift region of n-type located on a rear surface side with respect to the barrier region, separated from the body region by the barrier region, and having a density of n-type impurities lower than a density of n-type impurities in the barrier region;

a collector region of p-type exposed on the rear surface of the semiconductor substrate; and

a cathode region of n-type exposed on the rear surface of the semiconductor substrate and having a density of n-type impurities higher than the density of n-type impurities in the drift region,

the pillar region comprises a first portion extending from the barrier region along a direction toward the front surface of the semiconductor substrate and a second portion extending from the first portion along a direction moving away from the dummy trench,

the second portion is connected to the front surface electrode, and

an end portion of the first portion on a front surface side is not connected to the front surface electrode.

6. The semiconductor device of claim 5 , wherein the semiconductor substrate includes a plurality of gate trenches and a plurality of dummy trenches which are arranged alternately and repeatedly in a cross-section orthogonal to the front surface of the semiconductor substrate.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052285/0419 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2016
From: SENOO, MASARU; HIRABAYASHI, YASUHIRO
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 039661/0335 →
Priority Claims (1)
JP 2014-224247 · Nov 4, 2014 · national
Continuity (1)
Related Publication 20170250179A1 · Aug 31, 2017