IP Library Granted Patent US 10,019,933
Granted Patent B2
US 10,019,933 · App. 15/124,467 · Granted Jul 10, 2018

El display apparatus

Inventor: Hiroshi Takahara (Osaka, JP)
Assignee: JOLED INC.
G09G3/30G09G3/3233G09G3/3266G09G2300/0819G09G2300/0852G09G2310/0254G09G2310/0256G09G2310/0262G09G2310/0267G09G2310/0283G09G2310/0286G09G2310/0291G09G2320/043G09G2320/045
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Quick Facts
Patent No.
US 10,019,933
App. No.
15/124,467
Granted
Jul 10, 2018
Kind
B2
Abstract

An EL display apparatus includes pixels each including an EL element, a drive transistor, and a switch transistor, and further includes: a source driver circuit; a source signal line; a gate driver circuit; a first gate signal line; and a second gate signal line, wherein the gate driver circuit applies, to the first gate signal line, a first voltage or a second voltage, and the drive transistor is placed in a first state by the gate driver circuit applying the first voltage to the gate terminal of the drive transistor while the switch transistor is on, and is placed in a second state by the gate driver circuit applying the second voltage to the gate terminal of the drive transistor while the switch transistor is on.

Claims (31)

1. An electroluminescent (EL) display apparatus, comprising:

a display screen in which pixels are disposed in a matrix, the pixels each including an EL element, a drive transistor which supplies the EL element with a current, and a switch transistor having a source terminal and a drain terminal one of which is connected to a gate terminal of the drive transistor;

a source driver circuit which outputs a video signal to be applied to the pixels;

a source signal line for transmitting the video signal output by the source driver circuit to the gate terminal of the drive transistor;

a gate driver circuit which supplies the switch transistor with a control signal;

a first gate signal line for supplying the other of the source terminal and the drain terminal of the switch transistor with a voltage from the gate driver circuit; and

a second gate signal line for supplying the gate terminal of the switch transistor with the control signal from the gate driver circuit,

wherein the gate driver circuit applies, to the second gate signal line, an on voltage which places the switch transistor in an operating state or an off voltage which places the switch transistor in a non-operating state,

the gate driver circuit applies, to the first gate signal line, a first voltage or a second voltage, and

the drive transistor is placed in a first state by the gate driver circuit applying the first voltage to the gate terminal of the drive transistor while the switch transistor is on, and is placed in a second state by the gate driver circuit applying the second voltage to the gate terminal of the drive transistor while the switch transistor is on,

wherein the first voltage is a reference voltage (Vref) and the second voltage is a reverse bias voltage (Vnv).

2. The EL display apparatus according to claim 1 ,

wherein the first voltage is a positive voltage, and the second voltage is a negative voltage.

3. The EL display apparatus according to claim 1 ,

wherein the gate driver circuit places the first gate signal line in a high impedance state without outputting the first voltage and the second voltage, in between when the drive transistor is placed in the first state and when the drive transistor is placed in the second state.

4. A method for driving an electroluminescent (EL) display apparatus that includes

a display screen in which pixels are disposed in a matrix, the pixels each including an EL element, a drive transistor which supplies the EL element with a current, and a switch transistor which places the drive transistor in an operating state or a non-operating state;

a gate driver circuit which supplies the switch transistor with a voltage and a control signal for placing the switch transistor in an operating state or a non-operating state;

a first gate signal line for supplying the switch transistor with the voltage from the gate driver circuit; and

a second gate signal line for supplying the switch transistor with the control signal from the gate driver circuit, the method comprising:

placing the drive transistor in a first state by the gate driver circuit applying a first voltage to a gate terminal of the drive transistor while the switch transistor is in the operating state; and

placing the drive transistor in a second state by the gate driver circuit applying a second voltage to the gate terminal of the drive transistor while the switch transistor is in the operating state,

wherein the first voltage is a reference voltage (Vref) and the second voltage is a reverse bias voltage (Vnv).

5. The method according to claim 4 ,

wherein the first voltage output by the gate driver circuit is a positive voltage, and the second voltage output by the gate driver circuit is a negative voltage.

6. The method according to claim 4 ,

wherein the gate driver circuit places the first gate signal line in a high impedance state without outputting the first voltage and the second voltage, in between when the drive transistor is placed in the first state and when the drive transistor is placed in the second state.

7. The EL display apparatus according to claim 2 ,

wherein the gate driver circuit places the first gate signal line in a high impedance state without outputting the first voltage and the second voltage, in between when the drive transistor is placed in the first state and when the drive transistor is placed in the second state.

8. The method according to claim 5 ,

wherein the gate driver circuit places the first gate signal line in a high impedance state without outputting the first voltage and the second voltage, in between when the drive transistor is placed in the first state and when the drive transistor is placed in the second state.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2016
From: TAKAHARA, HIROSHI
To: JOLED INC.
Reel/Frame 039676/0943 →
Priority Claims (1)
JP 2014-050896 · Mar 13, 2014 · national
Continuity (1)
Related Publication 20170018220A1 · Jan 19, 2017