IP Library Granted Patent US 9,702,919
Granted Patent B2
US 9,702,919 · App. 15/125,332 · Granted Jul 11, 2017

Method for manufacturing display panel

Inventor: Mario Amatsuchi (Tokyo, JP)
Assignee: JOLED INC.
G01R31/022G01M11/0257G01M11/0264G01R31/02G01R31/26G01R31/2635G01R31/2639G09G3/2003
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,702,919
App. No.
15/125,332
Granted
Jul 11, 2017
Kind
B2
Abstract

A method for manufacturing a display panel including a display unit in which pixels, in rows and columns, include an organic EL element and a drive transistor, includes, performed on the display panel having a line defect which is a pixel column that emits light of luminance not reflecting display gray level signals: displaying, overlappingly, a lighted line, which is a pixel column inputted with uniform display gray level signals, and the line defect by displaying the lighted line on the display unit and scanning the display unit with the lighted line in the row direction; reducing a bright/dark part range in the line defect by uniformly changing the display gray level inputted to the pixel column in the lighted line overlapping with the line defect; and identifying a defective pixel, which is the line defect origin, from the position of the reduced bright/dark part range in the display unit.

Claims (18)

1. A method for manufacturing a display panel including a display unit in which a plurality of pixels, which emit light at a luminance reflecting display gray level signals that are inputted, are arranged in rows and columns, each of the plurality of pixels including a light-emitting element and a drive element that drives the light-emitting element, the method comprising the following, performed on the display panel having a line defect which is at least one of a pixel row and a pixel column that emits light at a luminance not reflecting the display gray level signals:

displaying a lighted line and the line defect overlapping each other by displaying the lighted line on the display unit and scanning the display unit with the lighted line in one of a row direction and a column direction, the lighted line being one of a pixel row and a pixel column that emits light when uniform display gray level signals are inputted;

reducing one of a bright part range and a dark part range in the line defect by uniformly changing, for all of the plurality of pixels included in the lighted line, one of (i) the uniform display gray level signals to be inputted to the lighted line displayed overlapping with the line defect and (ii) a drive power supply voltage that drives the drive element; and

identifying a defective pixel which is an origin of the line defect, from a position, in the display unit, of the one of the bright part range and the dark part range that has been reduced.

2. The method for manufacturing a display panel according to claim 1 ,

wherein, in the displaying, the reducing, and the identifying, the plurality of pixels not included in the lighted line are caused to stop emitting light.

3. The method for manufacturing a display panel according to claim 1 ,

wherein, in the reducing, the dark part range is reduced by raising a display gray level in the lighted line by one of (i) uniformly changing the uniform display gray level signals for the lighted line and (ii) uniformly increasing the drive power supply voltage for the lighted line, when the overlapping of the lighted line and the line defect in the displaying results in the lighted line having a display pattern that changes sequentially from bright to dark to bright, from one end of the lighted line to the other.

4. The method for manufacturing a display panel according to claim 1 ,

wherein, in the reducing, the bright part range is reduced by lowering a display gray level in the lighted line by one of (i) uniformly changing the uniform display gray level signals for the lighted line and (ii) uniformly decreasing the drive power supply voltage for the lighted line, when the overlapping of the lighted line and the line defect in the displaying results in the lighted line having a display pattern that changes sequentially from dark to bright to dark, from one end of the lighted line to the other.

5. The method for manufacturing a display panel according to claim 1 , further comprising:

forming the plurality of pixels on a substrate before the displaying; and

repairing the defective pixel after the identifying.

6. The method for manufacturing a display panel according to claim 5 , further comprising

aging the display panel and inspecting for presence of the defective pixel in the display unit after the aging, the aging and the inspecting being performed after the forming and before the displaying.

7. The method for manufacturing a display panel according to claim 1 ,

wherein a first source driver circuit is disposed at one end of the display unit and a second source driver circuit is disposed at another end of the display unit which is opposite the one end, the first source driver circuit and the second source driver circuit supplying the display gray level signals to the plurality of pixels, and

in the reducing, the one of the bright part range and the dark part range on the line defect is reduced by causing a non-conducting state between one of the first source driver circuit and the second source driver circuit and the plurality of pixels included in the lighted line, and, while supplying the uniform display gray level signals to all of the plurality of pixels included in the lighted line from the other of the first source driver circuit and the second source driver circuit, uniformly changing, for all of the plurality of pixels included in the lighted line, one of the uniform display gray level signals and the drive power supply voltage.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2016
From: AMATSUCHI, MARIO
To: JOLED INC.
Reel/Frame 039703/0679 →
Priority Claims (1)
JP 2014-052556 · Mar 14, 2014 · national
Continuity (1)
Related Publication 20170098398A1 · Apr 6, 2017