Input/output apparatus and method
An input/output apparatus according to the present invention has an indication unit and an execution unit. The indication unit indicates that each of a plurality of data blocks between a main memory and a buffer memory is to be transferred. The execution unit transfers one data block relating to a transfer indication sent from the indication unit. After the completion of the transfer, in order to send completion information relating to the one data block to the indication unit, the execution unit determines whether transfers of all of the plurality of data blocks are completed or not based on management information for managing progresses of the transfers of the plurality of data blocks. Once determining that all of the transfers are completed, the execution unit sends, to the indication unit, total completion information showing that all of the transfers are completed.
1. A host bus adapter (HBA), comprising:
a Large-Scale Integration (LSI) communicatively coupled to a Storage Area Network (SAN) and a bus of a computer, wherein the LSI includes an execution logic circuit and an indication logic circuit;
a memory that stores a plurality of tables and a plurality of buffers, wherein the plurality of tables includes a transmitted data management table and a transmission buffer table;
a plurality of Direct Memory Access (DMA) channels that are each associated with at least one of the plurality of buffers
wherein the indication circuit:
acquires frame transmission information for a record from the transmitted data management table, wherein the frame transmission information includes information that identifies a plurality of data blocks to be transferred,
determines a number of DMA channels required for the record according to the frame transmission information,
creates data block information for each of the plurality of data blocks based on the number of DMA channels required, wherein the data block information includes a final flag, and
transmits, to the execution logic circuit, the data block information for each of the number of DMA channels required for the record;
wherein the execution logic circuit:
receives the data block information for each of the number of DMA channels required for the record,
reserves secured DMA channels for the number of DMA channels required from the plurality of DMA channels,
concurrently executes, using the secured DMA channels, transfers of the plurality of data blocks from the bus to buffers associated with each of the secured DMA channels based on the data block information,
updates the transmission buffer table when each of the transfers is executed, wherein a completion flag for the record is set in the transmission buffer table based on the final flag, and
transmits a frame storage message to the indication circuit when the completion flag for the record is set;
wherein the indication circuit further:
receives the frame storage message and causes the execution circuit to transmit the plurality of data blocks from the buffers associated with each of the secured DMA channels to the SAN.
2. The HBA according to claim 1 , wherein the execution circuit further releases the plurality of buffers when the plurality of data blocks are transmitted to the SAN.
3. The HBA according to claim 1 , wherein the execution circuit further:
transmits completion information to the indication circuit after each of the transfers.
4. The HBA according to claim 3 , wherein, the completion information shows that transfers of all of data blocks corresponding to one buffer memory are completed.
5. An method for transferring data from a computer bus to a storage area network (SAN), the method comprising:
acquiring, by an indication circuit of a host bus adapter (HBA), frame transmission information for a record from a transmitted data management table stored in a memory of the HBA, wherein the frame transmission information includes information that identifies a plurality of data blocks to be transferred;
determining, by the indication circuit, a number of Direct Memory Access (DMA) channels required for the record according to the frame transmission information;
creating, by indication circuit, data block information for each of the plurality of data blocks based on the number of DMA channels required, wherein the data block information includes a final flag;
receiving, by an execution circuit of the HBA, the data block information for each of the number of DMA channels required for the record from the indication circuit;
reserving, by the execution circuit, secured DMA channels for the number of DMA channels required from a plurality of DMA channels;
concurrently executing, by the execution circuit, transfers of the plurality of data blocks from the bus to buffers associated with each of the secured DMA channels using the secured DMA channels based on the data block information;
updating, by the execution circuit, a transmission buffer table stored in the memory, HBA when each of the transfers is executed, wherein a completion flag for the record is set in the transmission buffer table based on the final flag;
receiving, by the indication circuit, a frame storage message from the execution circuit when the completion flag for the record is set; and
transmitting, by the execution circuit, the plurality of data blocks from the buffers associated with each of the secured DMA channels to the SAN in response to a message from the indication circuit.
6. A host bus adapter (HBA), comprising:
a Large-scale integration (LSI) communicatively coupled to a storage area network (SAN) and a bus of a computer, wherein the LSI includes an execution logic circuit and an indication logic circuit;
a memory that stores a plurality of tables and a plurality of buffers, wherein the plurality of tables includes a transmitted data management table and a transmission buffer table;
a plurality of DMA channels that are each associated with at least one of the plurality of buffers
wherein the indication circuit:
acquires frame transmission information for a record from the transmitted data management table, wherein the frame transmission information includes information that identifies a plurality of data blocks to be transferred,
determines a number of DMA channels required for the record according to the frame transmission information,
creates data block information for each of the plurality of data blocks based on the number of DMA channels required, wherein the data block information includes a final flag, and
transmits, to the execution logic circuit, the data block information for each of the number of DMA channels required for the record;
wherein the execution logic circuit: receives the data block information for each of the number of DMA channels required for the record,
reserves secured DMA channels for the number of DMA channels required from the plurality of DMA channels,
concurrently executes, using the secured DMA channels, transfers of the plurality of data blocks from the SAN to buffers associated with each of the secured DMA channels based on the data block information,
updates the transmission buffer table when each of the transfers is executed, wherein a completion flag for the record is set in the transmission buffer table based on the final flag, and
transmits a frame storage message to the indication circuit when the completion flag for the record is set;
wherein the indication circuit further:
receives the frame storage message and causes the execution circuit to transmit the plurality of data blocks from the buffers associated with each of the secured DMA channels to the bus.