Successive-approximation register (SAR) analog-to-digital converter (ADC) with ultra low burst error rate

1. A method, comprising:

applying analog-to-digital conversion, in a signal processing component, to an analog input via a plurality of successive conversion cycles, wherein each conversion cycle corresponds to a particular bit in a corresponding digital output;

for each one of the plurality of successive conversion cycles, triggering a next one of the plurality of successive conversion cycles based on a cycle termination event;

detecting meta-stability during each one of the plurality of successive conversion cycles;

retaining information relating to result of said detecting of meta-stability during each conversion cycle until end of the analog-to-digital conversion;

after completing all of the plurality of successive conversion cycles, assessing a meta-stability state based on retained information for results of all of the plurality of successive conversion cycles, wherein:

assessing meta-stability state of a conversion cycle is based on settling of a matching search for that conversion cycle; and

determining that meta-stability for that conversion cycle occurred based on a change in outcome of the matching search after triggering of a next conversion cycle; and

controlling the digital output based on the assessing.

2. The method of claim 1 , comprising determining that meta-stability for that conversion cycle occurred when the matching search fails to settle within a corresponding time period.

3. The method of claim 1 , wherein the cycle termination event comprises expiry of a corresponding fixed delay.

4. The method of claim 1 , wherein the controlling of the digital output comprises adjusting at least a portion of the digital output based on detection of a meta-stability event.

5. A system, comprising:

one or more circuits for use in a signal processing component, the signal processing component being configured to perform a plurality of processing operations, comprising analog-to-digital conversions, where the one or more circuits are operable to:

apply analog-to-digital conversion to an analog input via a plurality of successive conversion cycles, wherein each conversion cycle corresponds to a particular bit in a digital output of the conversion;

for each one of the plurality of successive conversion cycles, trigger a next one of the plurality of successive conversion cycles based on a cycle termination event;

detect meta-stability during each one of the plurality of successive conversion cycles, using a corresponding one of a plurality of meta-stability detectors;

retain via the plurality of meta-stability detectors information relating to result of said detecting of meta-stability during each conversion cycle until end of the analog-to-digital conversion;

after completing all of the plurality of successive conversion cycles, assess meta-stability state based on retained information for results of all of the plurality of successive conversion cycles; and

control the digital output based on the assessing.

6. The system of claim 5 , wherein the one or more circuits are operable to assess meta-stability state of a conversion cycle based on settling of a matching search for that conversion cycle.

7. The system of claim 6 , wherein the one or more circuits are operable to determine that meta-stability for that conversion cycle occurred when the matching search fails to settle within a corresponding time period.

8. The system of claim 6 , wherein the one or more circuits are operable to determine that meta-stability for that conversion cycle occurred based on a change in outcome of the matching search after triggering of a next conversion cycle.

9. The system of claim 5 , wherein the cycle termination event comprises expiry of a corresponding fixed delay.

10. The system of claim 5 , wherein the controlling of the digital output comprises adjusting at least a portion of the digital output based on detection of a meta-stability event.

11. A system, comprising:

an analog-to-digital convertor (ADC) operable to perform analog-to-digital conversions via a plurality of successive conversion cycles, wherein each conversion cycle corresponds to a particular bit in a digital output of the ADC, the ADC comprising:

a comparator circuit operable to generate in each conversion cycle an output based on comparison between two inputs corresponding to that conversion cycle;

a successive approximation register (SAR) circuit operable to record outcomes of bit-wise comparisons performed in the comparator circuit;

a controller circuit for controlling operation of the comparator circuit, the controlling comprising setting or adjusting the inputs to the comparator circuit; and

a meta-stability detector circuit that is operable to, for each one of the plurality of successive conversion cycles:

detect meta-stability during that conversion cycle;

retain information relating to result of said detecting until end of the analog-to-digital conversion;

trigger a next one of the plurality of successive conversion cycles based on a cycle termination event;

wherein the ADC is operable to:

after completing all of the plurality of successive conversion cycles, assess a meta-stability state based on retained information for results of all of the plurality of successive conversion cycles; and

control the digital output based on the assessing;

wherein:

the meta-stability detector circuit comprises a plurality of per-bit meta-stability detectors; and

each one of the plurality of per-bit meta-stability detectors is operable to store indication of result of meta-stability detection during a conversion cycle associated with a corresponding bit in the digital output based on settling of a corresponding comparison via the comparator circuit for that conversion cycle.

12. The system of claim 11 , wherein each one of the plurality of per-bit meta-stability detectors is operable to record information indicating occurrence of meta-stability when the matching search fails to settle within a corresponding time period.

13. The system of claim 11 , wherein each one of the plurality of per-bit meta-stability detectors is operable to record information indicating occurrence of meta-stability when there is a change in outcome of the comparison after triggering of a next conversion cycle.

14. The system of claim 11 , wherein the cycle termination event comprises expiry of a corresponding fixed delay; and

the meta-stability detector circuit comprises a timer circuit that is operable to generate a timing indication for the fixed delay.

15. The system of claim 11 , wherein the controller circuit is operable to enable the comparator circuit at a start of each conversion cycle based on the triggering.

16. The system of claim 11 , wherein the controller circuit is operable to control setting of the inputs to the comparator circuit based on an output of the comparator circuit from a prior conversion cycle.

17. The system of claim 11 , wherein the controlling of the digital output comprises adjusting at least a portion of the digital output based on detection of a meta-stability event.