Digital-to-analog converter (DAC) with digital offsets
View Patent ↗Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.
1. A method, comprising:
applying a digital offset to an input of a digital-to-analog converter (DAC); and
applying, via said DAC, digital-to-analog conversion to said input with said digital offset;
wherein:
said digital offset is fixed and pre-determined during design of said DAC;
said digital offset is set to account for one or more conditions relating to inputs to said DAC; and
said one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in said DAC, wherein each conversion element handles a particular bit in inputs to said DAC.
2. The method of claim 1 , comprising selectively applying one or more adjustments to said digital offset for particular input conditions.
3. The method of claim 1 , comprising determining said digital offset to modify said switching characteristics for at least one conversion element.
4. The method of claim 3 , wherein said modifying of said switching characteristics comprises eliminating switching transitions for at least one conversion element.
5. The method of claim 1 , wherein said one or more conditions comprise signal backoff.
6. The method of claim 1 , wherein said switching characteristics comprise, for each conversion element, whether said conversion element switches or not for particular input and/or conditions related to said particular input.
7. A system comprising:
a digital-to-analog converter (DAC) that is operable to apply digital-to-analog conversions, said DAC comprising a plurality of conversion elements with each conversion element configured to handle a particular bit in a digital input to said DAC, wherein said DAC is operable to:
apply a digital offset to an input to said DAC, wherein said digital offset is fixed and pre-determined during design of said DAC; and
apply digital-to-analog conversion to said input with said digital offset; and
wherein:
said digital offset is set to account for one or more conditions relating to inputs to said DAC; and
said one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in said DAC, wherein each conversion element handles a particular bit in inputs to said DAC.
8. The system of claim 7 , wherein said DAC is operable to selectively apply one or more adjustments to said digital offset for particular input conditions.
9. The system of claim 7 , wherein said DAC is operable to determine said digital offset to modify said switching characteristics for at least one conversion element.
10. The system of claim 9 , wherein said modifying of said switching characteristics comprises eliminating switching transitions for at least one conversion element.
11. The system of claim 7 , wherein said one or more conditions comprise signal backoff.
12. The system of claim 7 , wherein said switching characteristics comprise, for each conversion element, whether said conversion element switches or not for particular input and/or conditions related to said particular input.
13. The system of claim 7 , wherein said DAC comprises a plurality of segments, with each segment comprising one or more conversion elements of said plurality of conversion elements.
14. The system of claim 13 , wherein said plurality of segments comprises:
a most significant bits (MSBs) segment; and
one or more least significant bits (LSBs) segments.
15. The system of claim 14 , wherein said plurality of segments comprises:
a lower least significant bits (LLSBs) segment;
a middle least significant bits (MLSBs) segment; and
an upper least significant bits (ULSBs) segment.
16. The system of claim 14 , wherein digital said offset is determined based on switching characteristics of only one or more conversion elements in said MSBs segment.