High voltage integrated circuits having improved on-resistance value and improved breakdown voltage
A high voltage integrated device includes a semiconductor layer having a first conductivity, a source region having a second conductivity and a drift region having the second conductivity which are disposed in the semiconductor layer and spaced apart from each other by a channel region, a drain region having the second conductivity and disposed in the drift region, a gate insulation layer disposed over the channel region, a first field insulation layer and a second field insulation layer which are disposed over the drift region and between the channel region and the drain region, wherein the first field insulation layer and the second field insulation layer are spaced apart from each other, an insulation layer disposed over the drift region and located between the first and second field insulation layers, and a gate electrode disposed over the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer, wherein the first field insulation layer is adjacent to the channel region and the second field insulation layer is adjacent to the drain region.
1. A high voltage integrated device comprising:
a semiconductor layer having a first conductivity;
a source region having a second conductivity and a drift region having the second conductivity which are disposed in the semiconductor layer and spaced apart from each other by a channel region;
a drain region having the second conductivity and disposed in the drift region;
a gate insulation layer disposed over the channel region;
a first field insulation layer and a second field insulation layer which are disposed over the drift region and between the channel region and the drain region, wherein the first field insulation layer and the second field insulation layer are spaced apart from each other;
an insulation layer disposed over the drift region and located between the first and second field insulation layers; and
a gate electrode disposed over the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer,
wherein the first field insulation layer is adjacent to the channel region and the second field insulation layer is adjacent to the drain region.
2. The high voltage integrated device of claim 1 , further comprising:
a body region having the first conductivity, disposed in the semiconductor layer, and surrounding the source region,
wherein the body region is spaced apart from the drift region.
3. The high voltage integrated device of claim 2 , wherein the channel region includes:
a first channel region defined in an upper portion of the body region and between the source region and the semiconductor layer; and
a second channel region defined in an upper portion of the semiconductor layer and between the body region and the drift region.
4. The high voltage integrated device of claim 1 , wherein a top surface of the drift region is coplanar with a top surface of the channel region.
5. The high voltage integrated device of claim 1 , wherein the first and second field insulation layers have substantially the same thickness.
6. The high voltage integrated device of claim 1 , wherein a first sidewall of the first field insulation layer is in direct contact with a sidewall of the gate insulation layer.
7. The high voltage integrated device of claim 6 , wherein the first sidewall of the first field insulation layer is aligned with a first sidewall of the drift region, and
wherein the first sidewall of the drift region is in contact with the channel region.
8. The high voltage integrated device of claim 6 , wherein a first sidewall of the insulation layer is in direct contact with a second sidewall of the first field insulation layer, and
wherein a second sidewall of the insulation layer is in direct contact with a first sidewall of the second field insulation layer.
9. The high voltage integrated device of claim 8 , wherein a second sidewall of the second field insulation layer is aligned with a second sidewall of the drain region.
10. The high voltage integrated device of claim 1 , wherein each of the first and second field insulation layers have a sloped sidewall profile.
11. The high voltage integrated device of claim 1 , wherein a length of the first field Insulation layer, which is measured in a channel length direction, is substantially equal to a length of the second field insulation layer, which is measured in the channel length direction.
12. The high voltage integrated device of claim 1 , wherein a length of the second field insulation layer, which is measured in a channel length direction, is greater than a length of the first field insulation layer, which is measured in the channel length direction.
13. The high voltage integrated device of claim 12 , wherein the length of the second field insulation layer is at least 1.2 times longer than the length of the first field insulation layer.
14. The high voltage integrated device of claim 1 , wherein a thickness of the insulation layer is substantially equal to a thickness of the gate insulation layer.
15. The high voltage integrated device of claim 14 , wherein each of the first and second field insulation layers has a thickness greater than a thickness of the insulation layer.
16. The high voltage integrated device of claim 15 , wherein each of the first and second field insulation layers is at least thirty times thicker than the insulation layer.
17. The high voltage integrated device of claim 1 , wherein each of the first and second field insulation layers includes a high temperature oxide (HTO) layer.
18. The high voltage integrated device of claim 1 , wherein the gate insulation layer, the first field insulation layer, the insulation layer, and the second field insulation layer are arranged side by side at substantially the same level.