A/D converter including multiple sub-A/D converters
View Patent ↗An A/D converter includes: an input buffer; N sub-A/D converters including N first sampling circuits that are connected to the input buffer, and that sample the output analog signal in respective sampling slots; a control circuit that executes calibration for the N first sampling circuits one by one; a reference A/D converter including a second sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and a third sampling circuit that is connected to the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N−1) first sampling circuits out of the execution of the calibration.
1. An A/D converter comprising:
an input buffer that receives an analog signal and outputs an output analog signal;
N (an integer of two or more) sub-A/D converters including N first sampling circuits that are connected to an output side of the input buffer, and that sample the output analog signal in respective sampling slots different from each other;
a control circuit that executes calibration for the N first sampling circuits one by one;
a reference A/D converter including a second sampling circuit that is connected to the output side of the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of one first sampling circuit under execution of the calibration among the N first sampling circuits; and
a third sampling circuit that is connected to the output side of the input buffer, and that samples the output analog signal in the same sampling slots as the sampling slots of the (N−1) first sampling circuits out of the execution of the calibration.
2. The A/D converter according to claim 1 , further comprising a sub-A/D converter including the third sampling circuit.
3. The A/D converter according to claim 1 , wherein
the N first sampling circuits included in the N sub-A/D converters sample the output analog signal in turn in N successive sampling slots,
the one first sampling circuit under the execution of the calibration samples the output analog signal in a given sampling slot of the N successive sampling slots,
the (N−1) first sampling circuits out of the execution of the calibration sample the output analog signal in the respective (N−1) sampling slots of the N successive sampling slots,
the second sampling circuit included in the reference A/D converter samples the output analog signal in the given sampling slot, and
the third sampling circuit samples the output analog signal in the (N−1) sampling slots.
4. The A/D converter according to claim 3 , wherein
the third sampling circuit includes two samplers, and
the two samplers sample the output analog signal alternately in a time sharing manner in the (N−1) sampling slots in which the second sampling circuit does not perform sampling.
5. The A/D converter according to claim 3 , wherein
the third sampling circuit includes a single sampler,
the sampler includes a sampling switch that performs operation to sample the output analog signal, and
the sampling switch is kept on in a time period excluding the given sampling slot in which the second sampling circuit performs sampling.
6. An A/D converter comprising:
an input buffer that receives an analog signal and outputs an output analog signal;
N (an integer of two or more) sub-A/D converters including N first sampling circuits that are connected to an output side of the input buffer, and that sample the output analog signal in respective sampling slots different from each other during a calibration time frame in which calibration for the N first sampling circuits is to be executed and during an operational time frame other than the calibration time frame;
a control circuit that executes the calibration of the N first sampling circuits one by one;
a reference A/D converter including a second sampling circuit that is connected to the output side of the input buffer, and that samples the output analog signal in the same sampling slot as the sampling slot of each first sampling circuit under execution of the calibration during the calibration time frame; and
a third sampling circuit connected to the output side of the input buffer, wherein
the second sampling circuit and the third sampling circuit sample the output analog signal alternately in a time sharing manner in the sampling slots in which the N first sampling circuits sample the output analog signal during the operational time frame.