Pixel structure
A pixel structure includes a pixel unit layer and a first metal wire layer. Each of control signal line and first and second scan signal lines in the first metal wire layer is connected to each pixel unit in a corresponding row. An insulating layer is disposed between each first metal patterned section in the first metal wire layer and a corresponding row of pixel units. A second metal wire layer includes initial signal lines and second metal patterned sections. Each initial signal line is connected to each pixel unit in a corresponding row. Each second metal patterned section overlaps with one of the first metal patterned sections to form a capacitor. Each connection signal line in a third metal wire layer connects the first scan signal line of a current row of pixel units to the second scan signal line of a next row of pixel units.
1. A pixel structure comprising:
a pixel unit layer including a pixel unit array having a plurality of rows of pixel units and a plurality of columns of pixel units;
a first metal wire layer including a plurality of control signal lines, a plurality of first scan signal lines, a plurality of second scan signal lines, and a plurality of first metal patterned sections, wherein each of the plurality of control signal lines, the plurality of first scan signal lines, and the plurality of second scan signal lines is connected to each of the pixel units in a corresponding row, and each of the plurality of first metal patterned sections is disposed above a corresponding row of pixel units, and a first insulating layer is disposed between each of the plurality of first metal patterned sections and the corresponding row of pixel units;
a second metal wire layer including a plurality of initial signal lines and a plurality of second metal patterned sections, wherein each of the plurality of initial signal lines is connected to each of the pixel units in a corresponding row, and a portion of each of the plurality of second metal patterned sections is overlapped with one of the plurality of first metal patterned sections to form a first capacitor, and with a third insulating layer disposed between another portion of each of the plurality of second metal patterned sections which does not overlap with a corresponding one of the plurality of first metal patterned sections; and
a third metal wire layer including a plurality of connection signal lines connected to the first scan signal line of a current row of pixel units and to the second scan signal line of a next row of pixel units and a plurality of third metal patterned sections, with a portion of each of the plurality of third metal patterned sections overlapped with one of the plurality of second metal patterned sections to form a second capacitor connected to one of the first capacitors in parallel, and with a second insulating layer disposed between another portion of each of the plurality of third metal patterned sections which is not overlapped with a corresponding one of the plurality of second metal patterned sections.
2. The pixel structure as claimed in claim 1 , further comprising a control driving module mounted to a side of the pixel unit layer and connected to the plurality of control signal lines, wherein the control driving module is configured to generate a control signal transmitted through one of the plurality of control signal lines to the corresponding row of pixel units.
3. The pixel structure as claimed in claim 1 , further comprising a scan driving module mounted to each of two sides of the pixel unit layer, wherein the scan driving modules is connected to two ends of each of the plurality of first scan signal lines to generate a scan signal transmitted through one of the plurality of first scan signal lines to a corresponding pixel unit.
4. The pixel structure as claimed in claim 1 , further comprising a substrate and a buffer register layer disposed on the substrate, wherein the pixel unit layer, the first metal wire layer, the second metal wire layer, and the third metal wire layer are disposed on the buffer register layer.
5. The pixel structure as claimed in claim 4 , further comprising a second insulating layer disposed on an upper surface of the buffer register layer.
6. The pixel structure as claimed in claim 1 , further comprising a fourth metal wire layer including a plurality of data signal lines, wherein each of the plurality of data signal lines connected to a corresponding column of the pixel units.
7. The pixel structure as claimed in claim 6 , further comprising a data driving module mounted to a side of the pixel unit layer and connected to the plurality of data signal lines, wherein the data driving module is configured to generate a data signal transmitted through one of the plurality of data signal lines to the pixel units in the corresponding column.
8. The pixel structure as claimed in claim 1 , wherein each of the pixel units in the pixel unit array includes a pixel circuit having a pre-charging module, with the pre-charging module including an input end connected to a light-emitting diode and an output end connected to a first electrode of a pre-charging transistor, with the pre-charging transistor including a second electrode connected to the plurality of initial signal lines, and with the pre-charging transistor further including a gate connected to the plurality of second scan lines.