Processor and method of controlling execution of processes
A processor includes a plurality of processing sections, each of which executes a predetermined process. A plurality of fault detecting circuits are respectively provided for the plurality of processing sections, to detect a fault in one of the plurality of processing sections as a fault processing section to generate a fault detection signal. A fault monitoring and control section controls a normal processing section as at least one of the plurality of processing sections other than the fault processing section to execute a relieving process in response to the fault detection signal. The relieving process is determined based on a process load of the fault processing section, a process load of the normal processing section, and priority levels of processes to be executed by the fault processing section and the normal processing section.
1. A multi-processor system comprising:
a first processor;
a second processor;
a memory circuitry that is shared by the first and second processors, and that stores a first program for the first processor and a second program for the second processor;
a first bus coupled to the first processor; and
a first detecting circuitry that detects a bus error on the first bus,
wherein when the first detecting circuitry detects the bus error, the second processor interrupts a running process for the second program and determines whether to execute either the first program or the second program, and
wherein the multi-processor system is included in a single chip.
2. The multi-processor system according to claim 1 , further comprising:
a second bus coupled to the second processor; and
a second detecting circuitry that detects a bus error on the second bus.
3. The multi-processor system according to claim 1 , wherein the first detecting circuitry detects the bus error when data on the first bus indicate a predetermined value.
4. The multi-processor system according to claim 1 , wherein the first bus is a peripheral bus.
5. The multi-processor system according to claim 4 , wherein the peripheral bus is coupled to an input/output port to control an external system.
6. The multi-processor system according to claim 5 , wherein when the first detecting circuitry detects the bus error, the input/output port is disabled.
7. The multi-processor system according to claim 1 , wherein the second processor determines whether to execute either the first program or the second program based on priorities of the first and second programs.
8. The multi-processor system according to claim 1 , wherein the memory circuitry further stores a relieving program and the second processor executes the relieving program to determine whether to execute either the first program or the second program.