Circuit and method for detecting tampering or preventing forgery of semiconductor chip

1. A circuit for preventing forgery of a semiconductor chip, comprising:

a driving signal protection circuit portion comprising at least one protection wire for protecting a driving wire through which a driving signal of the semiconductor chip flows; and

a controller configured to:

generate a first security code and a second security code;

check whether the first security code that passes through the driving signal protection circuit portion and the second security code that bypasses the driving signal protection circuit portion correspond to each other to detect tampering at the at least one protection wire; and

control implementation of an operation of the semiconductor chip,

wherein, in response to a protection wire of the at least one protection wire being changed, the controller is further configured to assign a value to a corresponding bit of the first security code that is different from a corresponding bit of the second security code.

2. The circuit of claim 1 , wherein the controller is configured to generate a security code comprising at least one bit.

3. The circuit of claim 1 , wherein the controller is configured to check whether the first and second security codes match.

4. The circuit of claim 1 , wherein the controller is further configured to prevent a leakage current, and

wherein the changed protection wire of the at least one protection wire comprises a broken or tampered protection wire.

5. The circuit of claim 1 , wherein the controller is configured to assign a logic low value to the corresponding bit of the first security code by electrically connecting the changed protection wire to a ground voltage in response to the corresponding bit of the second security code being a logic high value.

6. The circuit of claim 1 , wherein the controller is configured to assign a logic high value to the corresponding bit of the first security code by electrically connecting the changed protection wire to a power supply voltage in response to the corresponding bit of the second security code being a logic low value.

7. The circuit of claim 1 , wherein, for the control of the semiconductor chip, the controller is configured to determine whether the semiconductor chip operates based on the first and second security codes.

8. The circuit of claim 7 , wherein the controller performs a predetermined operation that is different from an operation implemented by the driving signal when the first and second security codes do not match.

9. The circuit of claim 7 , wherein the controller stops the implemented operation of the semiconductor chip when the first and second security codes do not match.

10. The circuit of claim 1 , wherein the at least one protection wire is disposed adjacent to the driving wire.

11. The circuit of claim 2 , wherein the controller generates the security code such as a random code, a gray code, an add code, a reduce code or a cipher code according to a desired level of security.

12. The circuit of claim 11 , wherein the controller changes a type of the generated security code based on a predetermined condition while the semiconductor chip operates.

13. The circuit of claim 2 , wherein the controller is further configured to transform the generated security codes and provide the transformed security codes to the protection wire.

14. A method for preventing forgery of a semiconductor chip, the method comprising:

using at least one protection wire to protect a driving wire through which a driving signal of the semiconductor chip flows;

generating, by a controller, a first security code and a second security code;

checking, by the controller, whether the first security code passing through the at least one protection wire and the second security code bypassing the at least one protection wire correspond to each other to detect tampering that causes an induced change in the at least one protection wire; and

controlling, by the controller, implementation of an operation of the semiconductor chip based on a result of the checking,

wherein, in response to a protection wire of the at least one protection wire being changed, the controller being configured to electrically connect the changed protection wire to either a ground voltage or a power supply voltage so as to assign a value to a corresponding bit of the first security code that is different from a corresponding bit of the second security code.

15. The method of claim 14 , further comprising:

transforming the generated first and second security codes, and

providing the transformed first security code to the at least one protection wire and bypassing the transformed second security code.

16. A circuit for preventing forgery of a semiconductor chip, comprising:

a controller configured to:

control an operation of the semiconductor chip; and

generate a security code and copies of the security code; and

a driving signal protection circuit portion comprising protection wires and driving wires carrying data, the driving signal protection circuit portion receiving a first copy of the security code from the controller, and a second copy of the security code driven to bypass the driving signal protection circuit portion,

wherein the controller is further configured to:

in response to a protection wire of the protection wires being changed, assign a value to a corresponding bit of the first copy of the security code that is different from a corresponding bit of the second copy of the security code, and

check whether the first copy of the security code from the driving signal protection circuit portion and the second copy of the security code from the controller correspond to each other to detect tampering in response to the first copy of the security code not matching the second copy of the security code.

17. The circuit of claim 16 , wherein the controller is configured to:

assign a logic low value to the corresponding bit of the first copy of the security code by electrically connecting the changed protection wire to a ground voltage in response to the corresponding bit of the second copy of the security code being a logic high value, and

assign a logic high value to the corresponding bit of the first copy of the security code by electrically connecting the changed protection wire to a power supply voltage in response to the corresponding bit of the second copy of the security code being a logic low value.

18. The circuit for preventing of the semiconductor chip of claim 16 , wherein each of the protection wires is configured to break when physically touched.

19. The circuit for preventing of the semiconductor chip of claim 18 , wherein the protection wires are disposed around the driving wires.