Semiconductor devices and arrangements including dummy gates for electrostatic discharge protection
A semiconductor device and device arrangement including a plurality of semiconductor regions of different conductivity types and a plurality of gates which form electrically conducting paths between the semiconductor regions. The semiconductor device and device arrangement may be configured to protect against electrostatic discharge.
1. A semiconductor device, comprising:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type disposed adjacent to the first semiconductor region;
a third semiconductor region and a fourth semiconductor region of the second conductivity type disposed over or at least partially within the first semiconductor region, a fifth semiconductor region of the first conductivity type disposed between the third and fourth semiconductor regions, and a first gate disposed over the fifth semiconductor region;
a sixth semiconductor region and a seventh semiconductor region of the first conductivity type disposed over or at least partially within the second semiconductor region, an eighth semiconductor region of the second conductivity type disposed between the sixth and seventh semiconductor regions, and a second gate disposed over the eighth semi conductor region;
a plurality of dummy gates;
a first electrically conductive path leading from the third semiconductor region via a dummy gate of the plurality of dummy gates to the seventh semiconductor region, and
a second electrically conductive path leading from the sixth semiconductor region via another dummy gate of the plurality of dummy gates to the fourth semiconductor region.
2. The semiconductor device of claim 1 , wherein the plurality of dummy gates comprise a first, second, third, and fourth dummy gate,
wherein the first electrically conductive path leads from the third semiconductor region to the seventh semiconductor region via the first dummy gate and the second dummy gate coupled in series to the first dummy gate, and
wherein the second electrically conductive path leads from the sixth semiconductor region to the fourth semiconductor region via the third dummy gate and the fourth dummy gate coupled in series to the third dummy gate.
3. The semiconductor device of claim 2 , wherein the first and second dummy gates are disposed at opposite sides of the first gate, and
wherein the third and fourth dummy gates are disposed at opposite sides of the second gate.
4. The semiconductor device of claim 1 , wherein the fifth semiconductor region is of the same type as the first semiconductor region and the fifth semiconductor region comprises a dopant concentration smaller than the first semiconductor region.
5. The semiconductor device of claim 1 , wherein the eighth semiconductor region is of the same type as the second semiconductor region and the eighth semiconductor region comprises a dopant concentration smaller than the second semiconductor region.
6. A semiconductor device arrangement, comprising:
at least a first semiconductor device and a second semiconductor device, wherein each of the first and second semiconductor devices comprises:
a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type disposed adj acent to the first semiconductor region;
a third semiconductor region and a fourth semiconductor region of the second conductivity type disposed over or at least partially within the first semiconductor region, a fifth semiconductor region of the first conductivity type disposed between the third and fourth semiconductor regions, and a first gate disposed over the fifth semiconductor region;
a sixth semiconductor region and a seventh semiconductor region of the first conductivity type disposed over or at least partially within the second semiconductor region, an eighth semiconductor region of the second conductivity type disposed between the sixth and seventh semiconductor regions, and a second gate disposed over the eighth semi conductor region;
a plurality of dummy gates;
a first electrically conductive path leading from the third semiconductor region via a dummy gate of the plurality of dummy gates to the seventh semiconductor region, and
a second electrically conductive path leading from the sixth semiconductor region via another dummy gate of the plurality of dummy gates to the fourth semiconductor region;
wherein the first semiconductor region of the first semiconductor device is disposed adjacent to the second semiconductor region of the second semiconductor device, and
wherein the second semiconductor region of the first semiconductor device is disposed adjacent to the first semiconductor region of the second semiconductor device.
7. The semiconductor device arrangement of claim 6 , wherein the first and second semiconductor regions of the first and second semiconductor devices are arranged in a checkerboard-like arrangement.
8. The semiconductor device arrangement of claim 6 , wherein the fifth semiconductor region is of the same type as the first semiconductor region and the fifth semiconductor region comprises a dopant concentration smaller than the first semi conductor region.
9. The semiconductor device arrangement of claim 6 , wherein the eighth semiconductor region is of the same type as the second semiconductor region and the eighth semiconductor region comprises a dopant concentration smaller than the second semiconductor region.