Hetero-junction semiconductor device and method of manufacturing a hetero-junction semiconductor device
View Patent ↗A hetero-junction semiconductor device includes: a channel layer that includes a first semiconductor; a barrier layer that is provided on the channel layer and includes a semiconductor having a band gap larger than a band gap of the first semiconductor; a source electrode and a drain electrode that are provided on the barrier layer and are ohmic contacted to the barrier layer; a p-type semiconductor layer provided on the barrier layer, the p-type semiconductor layer being provided in a region between the source electrode and the drain electrode on the barrier layer; an n-type semiconductor layer that is provided on the p-type semiconductor layer; and a gate electrode that is joined to the n-type semiconductor layer. A joint interface between the p-type semiconductor layer and the n-type semiconductor layer has a concavo-convex structure.
1. A hetero-junction semiconductor device comprising:
a channel layer that includes a first semiconductor;
a barrier layer that is provided on the channel layer and includes a semiconductor having a band gap larger than a band gap of the first semiconductor;
a source electrode and a drain electrode that are provided on the barrier layer and are ohmic contacted to the barrier layer;
a p-type semiconductor layer provided on the barrier layer, the p-type semiconductor layer being provided in a region between the source electrode and the drain electrode on the barrier layer;
an n-type semiconductor layer that is provided on the p-type semiconductor layer; and
a gate electrode that is joined to the n-type semiconductor layer, wherein
a joint interface between the p-type semiconductor layer and the n-type semiconductor layer has a concavo-convex structure.
2. The hetero-junction semiconductor device according to claim 1 , wherein
in a convex region of the p-type semiconductor layer of the concavo-convex structure, the p-type semiconductor layer and the gate electrode are joined to each other through an insulating layer.
3. The hetero-junction semiconductor device according to claim 1 , wherein
the gate electrode is provided on a top surface of the n-type semiconductor layer and a side surface of the n-type semiconductor layer.
4. The hetero-junction semiconductor device according to claim 1 , wherein
a corner of the concavo-convex structure has a curved surface.
5. The hetero-junction semiconductor device according to claim 1 , wherein
the channel layer is composed of GaN,
the barrier layer is composed of AlGaN,
the p-type semiconductor layer is composed of p-type GaN, and
the n-type semiconductor layer is composed of n-type GaN.
6. The hetero-junction semiconductor device according to claim 1 , wherein
a width of a groove in the concavo-convex structure is set such that a depletion layer spreads over an entire convex region of the p-type semiconductor layer and an entire convex region of the n-type semiconductor layer.