System and method for operating a power converter

1. A power converter, comprising:

a first bus converter for converting a first DC bus voltage into a first high frequency alternating current (AC) voltage;

a second bus converter for converting a second high frequency AC voltage into a second DC bus voltage;

a resonant circuit for coupling the first bus converter and the second bus converter;

a controller for providing switching signals to the first bus converter and the second bus converter to operate the power converter in a soft switching mode, wherein the controller comprises:

a voltage detection circuit connected across at least one switching device of the power converter to detect a device voltage across the at least one switching device;

a hard switching pulse signal detector to generate hard switching detection pulses based on the device voltage and a reference voltage when a hard switching instance of the at least one switching device is detected;

a counter to count a number of hard switching detection pulses of the hard switching pulse signal detector;

a calculation module to update the number of hard switching detection pulses of the hard switching instances and to generate a new number of hard switching detection pulses;

a comparator to compare the new number of hard switching detection pulses with a threshold value and to provide a control signal if the new number exceeds the threshold value.

2. The power converter of claim 1 , wherein the voltage detection circuit includes a voltage divider circuit which generates the device voltage based on a ratio of resistors of the voltage divider.

3. The power converter of claim 1 , wherein the hard switching pulse signal detector comprises a comparator to compare the device voltage and the reference voltage and to generate a first detection signal.

4. The power converter of claim 3 , wherein the hard switching pulse signal detector further comprises a delay module to delay the first detection signal a delay time.

5. The power converter of claim 4 , wherein the hard switching pulse signal detector comprises a logic gate to compare the delayed first detection signal with a gate signal of the switching device to provide hard switching detection pulses.

6. The power converter of claim 1 , wherein the hard switching pulse signal detector comprises an optical transmitter to generate hard switching detection pulses.

7. The power converter of claim 6 , wherein the optical transmitter is connected between the voltage divider circuit and a reference voltage source having the reference voltage and generates hard switching detection pulses when the reference voltage is higher than the device voltage.

8. The power converter of claim 7 , wherein the hard switching pulse signal detector further comprises a current limiting resistor to limit the current through the optical transmitter.

9. The power converter of claim 7 , wherein the hard switching pulse signal detector comprises a blocking diode to block a current to flow from the voltage divider circuit to the reference voltage source.

10. The power converter of claim 1 , wherein the calculation module includes a multiplier to multiply the number of hard switching detection pulses with a per unit power of the power converter to generate the new number of hard switching detection pulses.

11. The power converter of claim 1 , wherein the control signal comprises a switching frequency command, a phase shift command, a dead time command, a trip signal command or combinations thereof.

12. The power converter of claim 11 , wherein the switching frequency command, the phase shift command and the dead time command are determined based on minimum and maximum limits.

13. A method of operating a power converter having a first bus converter coupled to a second bus converter by a resonant circuit, said method comprising:

detecting a device voltage across at least one switching device of the first bus converter or the second bus converter;

generating hard switching detection pulses based on the device voltage and a reference voltage when a hard switching instance of the at least one switching device is detected;

counting a number of hard switching detection pulses of the hard switching instances of the at least one switching device;

updating the number of hard switching detection pulses with a new number of hard switching detection pulses;

comparing the new number of hard switching detection pulses with a threshold value; and

generating a control signal if the new number of hard switching detection pulses exceeds the threshold value.

14. The method of claim 13 , wherein generating hard switching detection pulses includes comparing the device voltage and the reference voltage to generate a first detection signal.

15. The method of claim 13 , wherein generating hard switching detection pulses further includes delaying the first detection signal a delay time.

16. The method of claim 13 further comprising compare the delaying first detection signal with a gate signal of the switching device to provide hard switching detection pulses.

17. The method of claim 13 , wherein generating hard switching detection pulses includes providing a voltage difference of the reference voltage and the device voltage across a series connection of an optical transmitter, a current limiting resistor and a blocking diode.

18. The method of claim 13 , wherein updating the number of hard switching detection pulses comprises multiplying the number of hard switching detection pulses with a per unit power of the power converter to generate the new number of hard switching detection pulses.

19. The method of claim 13 , wherein the control signal comprises a switching frequency command, a phase shift command, a dead time command, a trip signal command or combinations thereof.