IP Library Granted Patent US 10,042,230
Granted Patent B2
US 10,042,230 · App. 15/143,853 · Granted Aug 7, 2018

Display device substrate, display device, electronic apparatus, control method for display device, and manufacturing method for display device substrate

Inventor: Takashi Miyata (Shiojiri, JP)
Assignee: Seiko Epson Corporation
G02F1/167G02F1/133382G09G3/344G02F2001/1676G09G2230/00G09G2300/0809G09G2310/0291G09G2320/0252G09G2320/041
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Quick Facts
Patent No.
US 10,042,230
App. No.
15/143,853
Granted
Aug 7, 2018
Kind
B2
Abstract

A display device substrate includes a pixel electrode including a first connection point and a second connection point and for applying a voltage to an electro-optical element, a display gradation of which changes according to application of a voltage, a first signal line, a second signal line, a first transistor configured to control connection of the first signal line and the first connection point, a second transistor configured to control connection of the second signal line and the second connection point, and an output section configured to supply a first driving signal to the first signal line and supply a second driving signal delayed with respect to the first driving signal to the second signal line.

Claims (30)

1. A display device substrate comprising:

a pixel electrode including a first connection point and a second connection point and for applying a voltage to an electro-optical element, a display gradation of which changes according to application of a voltage;

a first signal line;

a second signal line;

a first transistor configured to control connection of the first signal line and the first connection point;

a second transistor configured to control connection of the second signal line and the second connection point; and

an output section configured to supply a first driving signal to the first signal line and supply a second driving signal delayed with respect to the first driving signal to the second signal line, wherein

the output section includes a first inverter circuit that is electrically connected to the first signal line and a second inverter circuit that is electrically connected to the second signal line; and

the first inverter circuit includes a third transistor and the second inverter circuit includes a fourth transistor, a channel width of the fourth transistor being larger than a channel width of the third transistor.

2. The display device substrate according to claim 1 , further comprising a scanning line connected to a gate of the first transistor and a gate of the second transistor, wherein

the first transistor and the second transistor are controlled to an ON state according to supply of a selection voltage to the scanning line.

3. The display device substrate according to claim 1 , wherein

the output section includes a delay circuit that generates the second driving signal and outputs the second driving signal to the second signal line, and

the delay circuit includes a transistor having a characteristic that a drain current decreases as an environmental temperature is lower.

4. A display device comprising:

an electro-optical element, a display gradation of which changes according to application of a voltage;

a pixel electrode including a first connection point and a second connection point;

an opposite electrode configured to apply a voltage to the electro-optical element between the opposite electrode and the pixel electrode;

a first signal line;

a second signal line;

a first transistor configured to control connection of the first signal line and the first connection point;

a second transistor configured to control connection of the second signal line and the second connection point; and

an output section configured to supply a first driving signal to the first signal line and supply a second driving signal delayed with respect to the first driving signal to the second signal line, wherein

the output section includes a first inverter circuit that is electrically connected to the first signal line and a second inverter circuit that is electrically connected to the second signal line; and

the first inverter circuit includes a third transistor and the second inverter circuit includes a fourth transistor, a channel width of the fourth transistor being larger than a channel width of the third transistor.

5. An electronic apparatus comprising the display device according to claim 4 .

6. A control method for a display device including a pixel electrode including a first connection point and a second connection point and for applying a voltage to an electro-optical element, a display gradation of which changes according to application of a voltage, a first signal line, a second signal line, a first transistor configured to control connection of the first signal line and the first connection point, and a second transistor configured to control connection of the second signal line and the second connection point,

the control method for the display device comprising supplying, from an output section, a first driving signal to the first signal line and supplying, from the output section, a second driving signal delayed with respect to the first driving signal to the second signal line in a state in which the first transistor and the second transistor are turned on, wherein

the output section includes a first inverter circuit that is electrically connected to the first signal line and a second inverter circuit that is electrically connected to the second signal line; and

the first inverter circuit includes a third transistor and the second inverter circuit includes a fourth transistor, a channel width of the fourth transistor being larger than a channel width of the third transistor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2018
From: SEIKO EPSON CORPORATION
To: E INK CORPORATION
Reel/Frame 047072/0325 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2016
From: MIYATA, TAKASHI
To: SEIKO EPSON CORPORATION
Reel/Frame 038434/0386 →
Priority Claims (2)
JP 2015-094767 · May 7, 2015 · national
JP 2015-097112 · May 12, 2015 · national
Continuity (1)
Related Publication 20160329012A1 · Nov 10, 2016
Cited By (1)
US 12,339,560