IP Library Granted Patent US 9,748,478
Granted Patent B2
US 9,748,478 · App. 15/145,959 · Granted Aug 29, 2017

Memory device and method of manufacturing the same

Inventor: Yoshihisa Kagawa (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H01L45/085H01L27/112H01L27/24H01L45/12H01L45/124H01L45/1233H01L45/1246H01L45/1266H01L45/146H01L45/1625H01L45/1675
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Quick Facts
Patent No.
US 9,748,478
App. No.
15/145,959
Granted
Aug 29, 2017
Kind
B2
Abstract

A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.

Claims (7)

1. A method of manufacturing a memory device comprising the steps of:

forming an insulation layer on a lower electrode layer and opening a hole in the insulation layer reaching the lower electrode layer:

forming, on top surfaces of the insulation layer and surfaces of the hole, a nitride film or an oxide film of a metal element selected from Ti, Ta, Ru, Mn, Al, Co, or W, or an alloy of any of these metal elements, and which is thinner than a depth of the hole;

removing the nitride film or oxide film in a lower portion of the hole and exposing the lower electrode layer via the hole while leaving some of the nitride film or oxide film at least on sidewalls of the hole:

forming a first film that comes into contact with the lower electrode layer and with the nitride film or the oxide film and that is thinner than the depth of the hole;

forming, on the first film, a second film part of which is buried in the hole and which contains at least an element selected from Cu, Ag, Zn, Al, or-and-Zr, and at least one element selected from Te, S, or-and-Se;

planarizing a surface to remove portions of the nitride film or oxide film, the first film, and the second film, which are located on the insulation layer, with remainder portions of the nitride film or oxide film, the first film, and the second film in the hole being made to remain and forming a diffusion preventing barrier film that is made from the remainder portion of the nitride film or oxide film, a memory layer made from the remainder portion of the first film, and an ion source layer made from the remainder of the second film, and forming an upper electrode layer on the ion source layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2016
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 039240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2016
From: KAGAWA, YOSHIHISA
To: SONY CORPORATION
Reel/Frame 038786/0768 →
Priority Claims (1)
JP 2010-079695 · Mar 30, 2010 · national
Continuity (2)
Division 13048500 · Mar 15, 2011
Related Publication 20160248004A1 · Aug 25, 2016