Networked multi-interface host debugger
View Patent ↗A debugger is provided that is capable of connecting internally or externally to a host device using one or more of multiple host interfaces. The debugger can also connect, over a network, to a remote communication device executing a debugging application. Through the debugger, the debugging application receives messages from the host device regarding the status of a firmware on the host device, and sends debugging commands to the host device for performing operations such as updating the firmware on the host device.
1. A multiple host interface debugger for connecting to a host computing device via a plurality of internal host interfaces and one or more external host interfaces, the debugger comprising:
a network interface configured to receive a debugging command from a remote communication device, the network interface comprising one or more of a wired network interface, a wireless network interface, or a Universal Serial Bus (USB) interface;
a plurality of internal host interfaces configured for connecting the debugger to the host computing device via connections of the host computing device located internal to an enclosure of the host computing device, the plurality of internal host interfaces comprising a debug header and a Peripheral Component Interconnect (PCI) interface;
one or more external host interfaces configured for connecting the debugger to the host computing device via connections of the host device located external to the enclosure of the host computing device, the one or more external host interfaces comprising at least a USB interface;
a processor; and
a computer-readable medium with instructions stored thereon which, when executed by the processor, cause the apparatus to
receive the debugging command from the remote communication device connected via the network interface,
transmit the debugging command to the host device on one of the plurality of internal host interfaces if the debugger is configured to use one of the plurality of internal host interfaces for communicating with the host device, and
transmit the debugging command to the host device on one of the one or more external host interfaces if the debugger is configured to use one of the one or more external host interfaces for communicating with the host device.
2. The multiple host interface debugger of claim 1 , further comprising an enclosure containing the multiple host interface debugger, the enclosure comprising apertures for connecting to the one or more external host interfaces.
3. The multiple host interface debugger of claim 1 , wherein the debug header and the PCI interface are configured for simultaneous connection to the host device.
4. The multiple host interface debugger of claim 1 , wherein the PCI interface comprises a PCI card connector.
5. The multiple host interface debugger of claim 1 , further comprising an enclosure containing the multiple host interface debugger, the enclosure comprising apertures for connecting to the plurality of internal host interfaces.
6. The multiple host interface debugger of claim 1 , wherein the multiple host interface debugger is powered through the PCI interface.
7. The multiple host interface debugger of claim 1 , wherein the multiple host interface debugger is configured to turn on, turn off, or restart the host device.
8. A multiple host interface debugger for connecting to a host computing device via one or more internal host interfaces and one or more external host interfaces, the debugger comprising:
a network interface configured to receive a debugging command from a remote communication device, the network interface comprising one or more of a wired network interface, a wireless network interface, or a Universal Serial Bus (USB) interface;
one or more internal host interfaces configured for connecting the debugger to the host computing device via connections of the host computing device located internal to an enclosure of the host computing device, the one or more internal host interfaces comprising a debug header or a Peripheral Component Interconnect (PCI) interface;
one or more external host interfaces configured for connecting the debugger to the host computing device via connections of the host device located external to the enclosure of the host computing device, the one or more external host interfaces comprising at least a USB interface;
a processor; and
a computer-readable medium with instructions stored thereon which, when executed by the processor, cause the apparatus to
receive the debugging command from the remote communication device connected via the network interface,
transmit the debugging command to the host device on one of the one or more internal host interfaces if the debugger is configured to use one of the one or more internal host interfaces for communicating with the host device, and
transmit the debugging command to the host device on one of the one or more external host interfaces if the debugger is configured to use one of the one or more external host interfaces for communicating with the host device.
9. The multiple host interface debugger of claim 8 , further comprising an enclosure containing the multiple host interface debugger, the enclosure comprising apertures for connecting to the one or more external host interfaces.
10. The multiple host interface debugger of claim 8 , wherein the debug header and the PCI interface are configured for simultaneous connection to the host device.
11. The multiple host interface debugger of claim 8 , wherein the PCI interface comprises a PCI card connector.
12. The multiple host interface debugger of claim 8 , further comprising an enclosure containing the multiple host interface debugger, the enclosure comprising apertures for connecting to the one or more internal host interfaces.
13. The multiple host interface debugger of claim 8 , wherein the multiple host interface debugger is powered through the PCI interface.
14. The multiple host interface debugger of claim 8 , wherein the multiple host interface debugger is configured to turn on, turn off, or restart the host device.
15. A multiple host interface debugger for connecting to a host computing device via one or more internal host interfaces and one or more external host interfaces, the debugger comprising:
a network interface configured to receive a debugging command from a remote communication device;
one or more internal host interfaces configured for connecting the debugger to the host computing device via connections of the host computing device located internal to an enclosure of the host computing device;
one or more external host interfaces configured for connecting the debugger to the host computing device via connections of the host device located external to the enclosure of the host computing device;
a processor; and
a computer-readable medium with instructions stored thereon which, when executed by the processor, cause the apparatus to
receive the debugging command from the remote communication device connected via the network interface,
transmit the debugging command to the host device on one of the one or more internal host interfaces if the debugger is configured to use one of the one or more internal host interfaces for communicating with the host device, and
transmit the debugging command to the host device on one of the one or more external host interfaces if the debugger is configured to use one of the one or more external host interfaces for communicating with the host device.
16. The multiple host interface debugger of claim 15 , further comprising an enclosure containing the multiple host interface debugger, the enclosure comprising apertures for connecting to the one or more external host interfaces.
17. The multiple host interface debugger of claim 15 , wherein the one or more internal host interfaces comprises a debug header and a Peripheral Component Interconnect (PCI) interface, wherein the debug header and the PCI interface are configured for simultaneous connection to the host device.
18. The multiple host interface debugger of claim 17 , wherein the PCI interface comprises a PCI card connector.
19. The multiple host interface debugger of claim 17 , wherein the multiple host interface debugger is powered through the PCI interface.
20. The multiple host interface debugger of claim 15 , further comprising an enclosure containing the multiple host interface debugger, the enclosure comprising apertures for connecting to the one or more internal host interfaces.