IP Library Granted Patent US 9,899,282
Granted Patent B2
US 9,899,282 · App. 15/148,144 · Granted Feb 20, 2018

Robust high performance semiconductor package

Inventor: Wayne Partington (Worcester, MA)
Assignee: Infineon Technologies Americas Corp.
H01L23/057H01L23/24H01L23/3675H01L23/42H01L23/49838H01L23/562H01L25/0655H01L25/072H05K1/0216H01L25/162H01L25/18H05K1/117H05K2201/1034H05K2201/10295H05K2201/10371H05K2201/10424
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Quick Facts
Patent No.
US 9,899,282
App. No.
15/148,144
Granted
Feb 20, 2018
Kind
B2
Abstract

A semiconductor package includes a suspended substrate having one or more semiconductor devices thereon, a metallic case covering the suspended substrate, the suspended substrate being supported by a plurality of mechanical leads on opposing sides of the semiconductor package, at least one of the plurality of mechanical leads having a coefficient of thermal expansion (CTE) that substantially matches a CTE of the suspended substrate, where at least one of the plurality of mechanical leads is electrically connected to the suspended substrate, and where the plurality of mechanical leads absorb mechanical shocks so as to prevent damage to the semiconductor package. The semiconductor package also includes a thermal gel between the suspended substrate and the metallic case. The suspended substrate can be a printed circuit board. The metallic case includes mounting ears for transferring heat away from the semiconductor package.

Claims (37)

1. A semiconductor package comprising:

a suspended substrate having one or more semiconductor devices thereon;

a metallic case covering said suspended substrate, the metallic case comprising a metallic sidewall;

a first sidewall and a second sidewall disposed on opposite sides of the suspended substrate, the first and the second sidewalls comprising an insulating material, wherein a portion of the metallic sidewall overlaps a portion of the first sidewall;

a plurality of leads extending through the first sidewall and the second sidewall without directly contacting the metallic case, said suspended substrate being supported by the plurality of leads on opposing sides of said semiconductor package; and

at least one of said plurality of leads having a coefficient of thermal expansion (CTE) that substantially matches a CTE of said suspended substrate.

2. The semiconductor package of claim 1 wherein at least one of said plurality of leads is electrically connected to said suspended substrate.

3. The semiconductor package of claim 1 wherein each of said plurality of leads has a CTE that substantially matches a CTE of said suspended substrate.

4. The semiconductor package of claim 1 wherein said plurality of leads absorb mechanical shocks so as to prevent damage to said semiconductor package.

5. The semiconductor package of claim 1 further comprising a thermal gel between said suspended substrate and said metallic case.

6. The semiconductor package of claim 1 wherein said suspended substrate is a printed circuit board.

7. The semiconductor package of claim 1 wherein said metallic case includes mounting ears for transferring heat away from said semiconductor package.

8. A semiconductor package comprising:

a suspended substrate having one or more semiconductor devices thereon;

a metallic case covering said suspended substrate, the metallic case comprising a metallic sidewall;

a first sidewall and a second sidewall disposed on opposite sides of the suspended substrate, the first and the second sidewalls comprising an insulating material, wherein a portion of the metallic sidewall overlaps a portion of the first sidewall;

a plurality of leads extending through the first sidewall and the second sidewall without directly contacting the metallic case, said suspended substrate being supported by the plurality of leads on opposing sides of said semiconductor package;

at least one of said plurality of leads having a horizontal portion that extends under and is attached to said suspended substrate; and

said plurality of leads having a coefficient of thermal expansion (CTE) that substantially matches a CTE of said suspended substrate.

9. The semiconductor package of claim 8 wherein at least one of said plurality of leads is electrically connected to said suspended substrate.

10. The semiconductor package of claim 8 wherein each of said plurality of leads has a CTE that substantially matches a CTE of said suspended substrate.

11. The semiconductor package of claim 8 wherein said plurality of leads absorb mechanical shocks so as to prevent damage to said semiconductor package.

12. The semiconductor package of claim 8 further comprising a thermal gel between said suspended substrate and said metallic case.

13. The semiconductor package of claim 8 wherein said suspended substrate is a printed circuit board.

14. The semiconductor package of claim 8 wherein said metallic case includes mounting ears for transferring heat away from said semiconductor package.

15. A semiconductor package comprising:

a suspended substrate having one or more semiconductor devices thereon;

a metallic case covering said suspended substrate;

a first sidewall and a second sidewall disposed on opposite sides of the suspended substrate, the first and the second sidewalls comprising an insulating material, the first sidewall intersecting with a first sidewall of the metallic case, the second sidewall intersecting with a second sidewall of the metallic case;

a plurality of mechanical leads extending through the first sidewall and the second sidewall without directly contacting the metallic case, said suspended substrate being supported by the plurality of mechanical leads on opposing sides of said semiconductor package;

at least one of said plurality of mechanical leads having a vertical portion that extends through said suspended substrate; and

said plurality of mechanical leads having a coefficient of thermal expansion (CTE) that substantially matches a CTE of said suspended substrate.

16. The semiconductor package of claim 15 wherein at least one of said plurality of mechanical leads is electrically connected to said suspended substrate.

17. The semiconductor package of claim 15 wherein each of said plurality of mechanical leads has a CTE that substantially matches a CTE of said suspended substrate.

18. The semiconductor package of claim 15 wherein said plurality of mechanical leads absorb mechanical shocks so as to prevent damage to said semiconductor package.

19. The semiconductor package of claim 15 further comprising a thermal gel between said suspended substrate and said metallic case.

20. The semiconductor package of claim 15 wherein said suspended substrate is a printed circuit board.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2016
From: PARTINGTON, WAYNE
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 038485/0236 →
Continuity (2)
Provisional Application 62196799 · Jul 24, 2015
Related Publication 20170025319A1 · Jan 26, 2017