Nitride semiconductor device
A nitride semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer located on the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer; a p-type semiconductor layer located on the second nitride semiconductor layer; and a gate electrode located on the p-type semiconductor layer. A first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer. The first interface has a first barrier with respect to holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second interface has a second barrier with respect to the holes moving in a direction from the p-type semiconductor layer to the gate electrode. The second barrier is higher than the first barrier.
1. A nitride semiconductor switching device, comprising:
a first nitride semiconductor layer;
a second nitride semiconductor layer located on and being in direct contact with the first nitride semiconductor layer and having a band gap larger than a band gap of the first nitride semiconductor layer;
a p-type semiconductor layer protruding from and being in direct contact with the second nitride semiconductor layer; and
a gate electrode located on and being in direct contact with the p-type semiconductor layer, the gate electrode comprising a first portion and a second portion, the first portion comprising a first material that is different from a second material of the second portion and wherein the first portion is partially surrounded by the second portion,
wherein
a first interface and a second interface are located in parallel between the gate electrode and the p-type semiconductor layer,
the first portion is in ohmic contact with the p-type semiconductor layer at the first interface, and
the second portion is in Schottky contact with the p-type semiconductor layer at the second interface and at least one side wall of the second portion is aligned with at least one side wall of the p-type semiconductor layer.
2. The nitride semiconductor switching device of claim 1 , wherein the first interface and the second interface are adjacent to each other.
3. The nitride semiconductor switching device of claim 2 , wherein
the first interface is provided within a range of a distance L 1 (m) from the second interface,
the distance L 1 , a dielectric constant ∈ s (Fm 31 1 ) of the p-type semiconductor layer, a built-in potential Vbi (V) of the second interface, a maximum rated gate voltage Vgm (V), an elementary electric charge q (C), and a p-type impurity density Na (m 31 3 ) in the p-type semiconductor layer satisfy the formula:
L
1
=
2
ɛ
s
(
Vbi
+
Vgm
)
qNa
.
4. The nitride semiconductor switching device of claim 3 , wherein
the first interface is provided within a range of a distance L 2 (m) from the second interface,
the distance L 2 , the dielectric constant ∈ s , the built-in potential Vbi, the elementary electric charge q, the p-type impurity density Na, and a gate threshold voltage Vgth (V) satisfy the formula:
L
2
=
2
ɛ
s
(
Vbi
+
Vgth
)
qNa
.
5. The nitride semiconductor switching device of claim 1 , wherein
the p-type semiconductor layer comprises a low density region and a high density region having a p-type impurity density higher than a p-type impurity density of the low density region,
the gate electrode is in contact with the low density region and the high density region,
the first interface is provided at an interface between the high density region and the gate electrode, and
the second interface is provided at an interface between the low density region and the gate electrode.
6. The nitride semiconductor switching device of claim 1 , further comprising:
a source electrode located on the second nitride semiconductor layer, and
a drain electrode located on the second nitride semiconductor layer,
wherein
the p-type semiconductor layer is located between the source electrode and the drain electrode.
7. The nitride semiconductor switching device of claim 1 , further comprising:
a source electrode located on a front surface of the second nitride semiconductor layer,
a drain electrode located on a rear surface of the first nitride semiconductor layer, and
a p-type separation region located inside the first nitride semiconductor layer,
wherein
the first nitride semiconductor layer comprises:
a first portion located on a front surface side of the p-type separation region;
a second portion located on a rear surface side of the p-type separation region; and
a connection portion connecting the first portion and the second portion,
the source electrode is located at a position on the front surface side of the p-type separation region, and
the p-type semiconductor layer is located at a position on the front surface side of the connection portion.